DS05-11045-1E

• Single +3.3 V Supply ±0.3 V tolerance
• LVTTL compatible I/O
• 4 K refresh cycles every 65.6 s
• Four bank operation
• Burst read/write operation and burst read/single write operation capability
• Standard and low power versions
• Programmable burst type, burst length, and CAS latency
• Auto-and Self-refresh (every 16 ms)
• CKE power down mode
• Output Enable and Input Data Mask

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

DS05-11045-1E is a CMOS Synchronous Dynamic Random Access Memory (SDRAM) containing 67,108,864 memory cells accessible in a 16-bit format. DS05-11045-1E features a fully synchronous operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. DS05-11045-1E is designed to reduce the complexity of using a standard dynamic RAM (DRAM) which requires many control signal timing constraints, and may improve data bandwidth of memory as much as 5 times more than a standard DRAM. DS05-11045-1E is ideally suited for workstations, personal computers, laser printers, high resolution graphic adapters/accelerators and other applications where an extremely large memory and bandwidth are required and where a simple interface is needed.