CXK77V1810GB-9

Features: • High speed, low power consumption• Single +3.3V power supply: 3.3V ± 5%• Inputs and outputs are LVTTL/LVCMOS-compatible• Byte Select capability• Asynchronous OE• Common data input and output• 9ns cycle time (110MHz)• All inputs (except OE...

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CXK77V1810GB-9 Picture
SeekIC No. : 004318738 Detail

CXK77V1810GB-9: Features: • High speed, low power consumption• Single +3.3V power supply: 3.3V ± 5%• Inputs and outputs are LVTTL/LVCMOS-compatible• Byte Select capability• Asynchronou...

floor Price/Ceiling Price

Part Number:
CXK77V1810GB-9
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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268 Transactions

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evaluate  (4.8 stars)

Upload time: 2024/11/23

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Product Details

Description



Features:

• High speed, low power consumption
• Single +3.3V power supply: 3.3V ± 5%
• Inputs and outputs are LVTTL/LVCMOS-compatible
• Byte Select capability
• Asynchronous OE
• Common data input and output
• 9ns cycle time (110MHz)
• All inputs (except OE) and outputs are registered on a single clock edge
• Self-timed write cycle
• Package line-up:
   - GB: 7 x 17 Plastic Ball Grid Array with 50mil pitch
   - TM: 400mil, 50-pin TSOP II with .8mm pitch



Pinout

  Connection Diagram


Specifications

Item
Symbol
Rating
Unit
Supply voltage
VDD
0.5 to +4.6
V
Input voltage
VIN
-0.5 to VCC+0.5 (4.6V max.)
V
Output Voltage
VO
-0.5 to VCC+0.5 (4.6V max.)
V
Allowable power dissipation
PD
1.0
W
Operating temperature
Topr
0 to 70
Storage temperature
Tstg
-55 to 150
Soldering temperature • time Tsolder
260 • 10
• sec




Description

The CXK77V1810GB-9 is a high-speed CMOS synchronous static RAM with common I/O pins, organized as 65,536-words-by-18-bits. This synchronous SRAM integrates input registers, high-speed SRAM and output registers onto a single monolithic IC. All input signals, except OE, are latched at the positive edge of an external clock (CLK). The RAM data from the previous cycle is presented at the positive edge of the subsequent clock cycle. Write operation is initiated by the positive edge of CLK and is internally self-timed. This feature eliminates complex off-chip write pulse generation and provides increased flexibility for incoming signals. Asynchronous OE adds the flexibility of data bus control. 100MHz operation CXK77V1810GB-9 is obtained from a single 3.3V power supply.




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