CXK77K36R320GB

The CXK77K36R320GB is a high speed CMOS synchronous static RAM with common I/O pins, organized as 1,048,576 words by 36 bits. This synchronous SRAM integra tes input registers, high speed RAM, output registers, and a one-deep write buffer onto a single monolithic IC. Register - Register (R-R) read operations and Late Write (LW) write operations are supported, providing a high-performance user interface.

All address and control input signals except G (Output Enable) and ZZ (Sleep Mode) CXK77K36R320GB are registered on the rising edge of the K differential input clock.

During read operations CXK77K36R320GB, output data is driven valid from the rising edge of K, one full clock cycle after the address is registered.

During write operations CXK77K36R320GB, input data is registered on the rising edge of K, one full clock cycle after the address is registered.

Sleep (power down) capability is provided via the ZZ input signal.

Output drivers CXK77K36R320GB are series terminated, and output impedance is programmable via the ZQ input pin. By connecting an external control resistor RQ between ZQ and V_SS, the impedance of the output drivers can be precisely controlled.

333 MHz operation CXK77K36R320GB is obtained from a single 2.5V power supply. JTAG boundary scan interface is provided using a subset of IEEE standard 1149.1 protocol.