Features: R-R Mode R-L, R-FT Modes
• Fast Cycle / Access Time tKHKH / tKHQV tKHKH / tKHQV
--------------------------------- ------------------ ------------------
-33 3.3ns / 2.3ns 5.0ns / 5.0ns
-37 3.6ns / 2.4ns 5.3ns / 5.3ns
-5 5.0ns / 2.5ns 5.3ns / 5.3ns
-6 6.0ns / 2.5ns 6.0ns / 6.0ns
• Single 3.3V power supply (VDD): 3.3V ± 5%
• Register - Register (R-R), Register - Latch (R-L), or Register - Flow Thru (R-FT) read operations
• Read operation protocol selectable via dedicated mode pins (M1, M2)
• Fully coherent, late write, self-timed write operations
• Byte Write capability
• Differential input clocks (K/K)
• Asynchronous output enable (G)
• Dedicated output supply voltage (VDDQ): 2.5V or 3.3V typical
• LVTTL/LVCMOS-compatible I/O interface
• Sleep (power down) mode via dedicated mode pin (ZZ)
• JTAG boundary scan (subset of IEEE standard 1149.1)
• 119 pin (7x17), 1.27mm pitch, 14mm x 22mm Plastic Ball Grid Array (PBGA) packageSpecifications
| Item |
Symbol |
Rating |
Unit |
| Supply voltage |
VDD |
0.5 to +4.6 |
V |
| Output Supply Voltage |
VDD |
0.5 to +4.6 |
V |
| Input voltage |
VIN |
-0.5 to VDD+0.5 (4.6V max.) |
V |
| Output Supply Voltage |
VOUT |
-0.5 to VDDQ+0.5 (4.6V max.) |
V |
| Operating temperature |
TA |
0 to 85 |
|
| Junction Temperature |
TJ |
0 to +110 |
|
| Storage temperature |
TSTG |
-55 to 150 |
|
(1)Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions other than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.DescriptionThe CXK77B3641AGB (organized as 131,072 words by 36 bits) and the CXK77B1841A (organized as 262,144 words by 18 bits) are high speed BiCMOS synchronous static RAMs with common I/O pins. These synchronous SRAMs integrate input registers, high speed RAM, output registers/latches, and a one-deep write buffer onto a single monolithic IC. Three distinct read operation protocols, Register - Register (R-R), Register - Latch (R-L), and Register - Flow Thru (R-FT), and one write operation protocol, Late Write (LW), are supported, providing a flexible, high-performance user interface.
All address, data CXK77B3641AGB, and control input signals except G (Output Enable) and ZZ (Sleep Mode) are registered on the positive edge of K clock. Read operation protocol is selectable through external mode pins M1 and M2.
Write operations CXK77B3641AGB are internally self-timed, eliminating the need for complex off-chip write pulse generation. In Register - Latch and Register - Flow Thru modes, when SW (Global Write Enable) is driven active, the subsequent positive edge of K clock tristates the SRAM's output drivers immediately, allowing Read-Write-Read operations to be initiated consecutively, with no dead cycles between them.
Sleep (power down) mode control CXK77B3641AGB is provided through the asynchronous ZZ input. 300 MHz operation is obtained from a single 3.3V power supply. JTAG boundary scan interface is provided using a subset of IEEE standard 1149.1 protocol.
CXK77B3641AGB Data Sheet
