Features: R-R Mode R-L, R-FT Modes
• Fast Cycle/Access Time tKHKH / tKHQV tKHKH / tKHQV
CXK77B1841 -45 4.5ns / 2.4ns 5.5ns / 5.5ns
-5 (*) 5.0ns / 2.5ns 5.7ns / 5.7ns
-6 6.0ns / 3.0ns 6.0ns / 6.0ns
Note (*): Contact Sony Memory Marketing for availability of "-5" speed bin.
• 3 synchronous modes of operation, selectable by mode pins:
Register-Register; Register-Latch; Register-Flow Thru;
• Single +3.3V power supply: 3.3V ± 5%
• Dedicated output supply voltage: VDDQ (2.5V to 3.3V typical)
• Inputs and outputs are LVTTL/LVCMOS compatible.
• Differential clock input (K/K). Clock levels are compatible to PECL, LVTTL and LVCMOS.
• All inputs (except asynchronous G and ZZ) and outputs are registered on a single clock edge.
• Byte Write capability.
• Late Write scheme to eliminate one dead cycle from Read-to-Write transitions.
• Self-timed write cycles.
• Sleep (power down) mode.
• JTAG boundary scan (subset of IEEE standard 1149.1).
• 119 pin (7x17) Plastic Ball Grid Array (PBGA) package.Specifications
| Item |
Symbol |
Rating |
Unit |
| Supply voltage |
VDD |
0.5 to +4.6 |
V |
| Output Supply Voltage |
VDD |
0.5 to +4.6 |
V |
| Input voltage |
VIN |
-0.5 to VDD+0.5 (4.6V max.) |
V |
| Output Supply Voltage |
VOUT |
-0.5 to VDDQ+0.5 (4.6V max.) |
V |
| Operating temperature |
TA |
0 to 70 |
|
| Junction Temperature |
TJ |
0 to +110 |
|
| Storage temperature |
TSTG |
-55 to 150 |
|
(1)Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions other than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.DescriptionThe CXK77B1841GB is a high speed BiCMOS synchronous static RAM with common I/O pins, organized as 262,144-words by 18-bits. This synchronous SRAM integrates input registers, high speed RAM, output registers/latches, and a one-deep write buffer onto a single monolithic IC. Three different read protocols - Register-Register (R-R), Register-Latch (R-L), and Registe r- Flow Thru (R-FT), and an enhanced write protocol - Late (Delayed) Write (LW), are supported, providing a flexible, high-performance user interface.
All input signals exceptG (Output Enable) and ZZ (Sleep Mode) CXK77B1841GB are registered on the positive edge of K clock.
Read cycles CXK77B1841GB can be controlled in one of three ways - with registered outputs in Register-Register mode, with latched outputs in Register-Latch mode, or with flow-through outputs in Register-Flow Thru mode. The read protocol is user-selectable through external mode pins M1 and M2.
Write cycles follow a Late Write protocol, where data CXK77B1841GB is provided to the SRAM one clock cycle after the address and control signals, eliminating one dead cycle from Read-to-Write transitions. In this scheme, when a write cycle is initiated, the address and data stored in the SRAM's write buffer during the previous write cycle are directed to the SRAM's memory core, while, simultaneously, the address and data from the current write cycle are stored in the SRAM's write buffer. In both Register-Latch and Register-Flow Thru modes, when SW (Global Write Enable) is driven active, the subsequent positive edge of K clock tristates the SRAM's output drivers immediately, allowing consecutive Read-Write-Read operations. The write cycle is internally self-timed, which eliminates complex off-chip write pulse generation and provides increased flexibility for incoming signals.
Sleep (power down) mode control CXK77B1841GB is provided through the asynchronous ZZ input. 220 MHz operation is obtained from a single 3.3V power supply. JTAG boundary scan interface is provided using a subset of IEEE standard 1149.1 protocol.
CXK77B1841GB Data Sheet
