Features: • Pin compatible with AS7C4098
• Industrial and commercial temperature
• Organization: 262,144 words * 16 bits
• Center power and ground pins
• High speed
- 10/12/15/20 ns address access time
- 5/6 ns output enable access time
• Low power consumption: ACTIVE
- 990mW/max @ 10 ns
• Low power consumption: STANDBY
- 55mW/max CMOS
• Individual byte read/write controls
• Easy memory expansion with CE, OE inputs
• TTL- and CMOS-compatible, three-state I/O
• 44-pin JEDEC standard packages
- 400-mil SOJ
- TSOP 2
• ESD protection 2000 volts
• Latch-up current 200 mASpecifications
|
Parameter |
Symbol |
Min |
Max |
Unit |
| Voltage on VCC relative to GND |
Vt1 |
-0.5 |
+7.0 |
V |
| Voltage on any pin relative to GND |
Vt2 |
-0.5 |
VCC + 0.5 |
V |
| Power Dissipation |
Pd |
- |
1.5 |
W |
| DC current into outputs (low) |
IOUT |
- |
±20 |
mA |
| Storage temperature (plastic) |
Tstg |
65 |
+150 |
°C |
| Ambient temperature with VCC applied |
Tbias |
55 |
+125 |
°C |
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied.Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DescriptionThe AS7C4098A is a high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as
262,144 words * 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access of AS7C4098A and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5/6 ns are ideal for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory systems.
When CE is high the device enters standby mode. AS7C4098A is guaranteed not to exceed 55mW power consumption in CMOS standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O1I/O16 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices of AS7C4098A should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle of AS7C4098A is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode.
AS7C4098A provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O1I/O8, and UB controls the higher bits, I/O9I/O16.
All chip inputs and outputs are TTL- and CMOS-compatible, and operation is for 5.0V (AS7C4098A) supply. The device is available in the JEDEC standard 400-mL, 44-pin SOJ, TSOP 2 packages.
AS7C4098A Data Sheet
