AS7C1024A-20STC

Features:

` AS7C1024A (5V version)
` AS7C31024A (3.3V version)
` Industrial and commercial temperatures
` Organization: 131,072 words x 8 bits
`High speed
- 10/12/15/20 ns address access time
- 5, 6, 7, 8 ns output enable access time
` Low power consumption: ACTIVE
- 853 mW (AS7C1024A) / max @ 10 ns
- 522 mW (AS7C31024A) / max @ 10 ns
` Low power consumption: STANDBY
- 55 mW (AS7C1024A) / max CMOS
- 36 mW (AS7C31024A) / max CMOS
` Latest 6T 0.25u CMOS technology
` Easy memory expansion with CE1 , CE2, OE  inputs
` TTL/LVTTL-compatible, three-state I/O
` 32-pin JEDEC standard packages
- 300 mil SOJ
- 400 mil SOJ
-8 * 20mm TSOP 1
- 8 x 13.4mm sTSOP 1
` ESD protection 2000 volts
`Latch-up current 200 mA

Pinout




Specifications

Parameter		Symbol	Min	Max	Unit
Voltage on VCC relative to GND	AS7C1024A	Vt1	-0.50	+7.0	V
	AS7C31024A	Vt1	0.50	+5.0
Voltage on any I/O pin relative to GND	Both	Vt2	0.50	VCC+ 0.50	V
Power dissipation	Both	PD		1.0	W
Storage temperature (plastic)	Both	Tstg	65	+150
Temperature with VCC applied	Both	Tbias	55	+125
DC output current (low)	Both	IOUT		20	mA

Description

The  AS7C1024A and AS7C31024A is a high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 131,072 words x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.

Equal address access of AS7C1024A-20STC and cycle times (t_AA , t _RC , t_WC ) of 10/12/15/20 ns with output enable access times (t_OE  ) of 5/6/7/8 ns are ideal for high performance applications. Active high and low chip enables (CE1 , CE2) permit easy memory expansion with multiple-bank systems.

When CE1 is high the devices enter standby mode. If inputs are still toggling, the device will consume I  power. If the bus is SB static, then full standby power is reached (I_SB1 ). For example, the  AS7C31024A is guaranteed not to exceed 55mW under nominal full standby  conditions.

A write cycle is accomplished by asserting write enable (WE ) and both chip enables (CE1 , CE2). Data on the input pins I/O0 through I/O7 is written on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1  or CE2 (write cycle 2).To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE ).

A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1 , CE2), with write enable (WE ) high. The chips drive I/O pins with the data word referenced by the input address. When either chip enable is inactive, output enable is inactive, or write enable is active,output drivers stay in high-impedance mode.