AS7C3364NTF32B-80TQCN

Features:

• Organization: 65,536 words × 32 or 36 bits
•NTD™architecture for efficient bus operation
• Fast clock to data access: 7.5/8.0/10.0 ns
•Fast OE access time: 3.5/4.0 ns
• Fully synchronous operation
• Flow-through mode
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Byte write enables
• Clock enable for operation hold 
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate VDDQ
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation


Pinout




Specifications

Parameter	Symbol	Min	Max	Unit
Power supply voltage relative to GND	VDD, VDDQ	0.5	+4.6	V
Input voltage relative to GND (input pins)	VIN	0.5	VDD + 0.5	V
Input voltage relative to GND (I/O pins)	VIN	0.5	VDDQ + 0.5	V
Power dissipation	Pd		1.8	W
Short circuit output current	IOUT		20	mA
Storage temperature	Tstg	65	+150
Temperature under bias	Tbias	65	+135

Description

The AS7C3364NTF32B/36B family is a  high performance CMOS 2 Mbit synchronous Static Random Access Memory (SRAM) organized as 65,536 words × 32 or 36 bits and incorporates a LATE Write.

This variation of the 2Mb+ synchronous SRAM uses the No Turnaround Delay (NTD™) architecture, featuring an enhanced write operation that improves bandwidth over flowthrough burst devices. In a normal flowthrough burst device, the write data, command, and address of AS7C3364NTF32B-80TQCN  are all applied to the device on the same clock edge. If a read command follows this write command, the system must wait for one dead cycle for valid data to become available. AS7C3364NTF32B-80TQCN dead cycle can significantly reduce overall bandwidth for applications requiring random access or read-modify write operations.