AS7C33512NTD18A

This variation of the 8Mb sychronous SRAM uses the No Turnaround Delay (NTD™) architecture, featuring an enhanced Write operation that improves bandwidth over pipeline burst devices. In a normal pipeline burst device, the write data, command, and address are all applied to AS7C33512NTD18A on the same clock edge. If a Read command follows this Write command, the system must wait for two 'dead' cycles for valid data to become available. These dead cycles of AS7C33512NTD18A can significantly reduce overall bandwidth for applications requiring random access or Read-Modify-Write operations.

NTD™ AS7C33512NTD18A devices use the memory bus more efficiently by introducing a write 'latency' which matches the two cycle pipeline (flowthrough) read latency. Write data is applied two cycles after the Write command of AS7C33512NTD18A and address, allowing the Read pipeline to clear. With NTD™, Write and Read operations can be used in any order without producing dead bus cycles.

Assert R/W low to perform Write cycles. Byte Write enable controls write access to specific bytes, or can be tied low for full 18 bit writes. Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data of AS7C33512NTD18A is applied to the device two clock cycles later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write operations; AS7C33512NTD18A can be tied low for normal operations. Outputs go to a high impedance state when the device is deselected by any of the three chip enable inputs (refer to Synchronous truth table on page 6). In pipeline mode, a two cycle deselect latency allows pending read or write operations to be completed.

Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is high, external addresses, chip select, R/W pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any device operations, including burst,AS7C33512NTD18A  can be stalled using the CEN=1 the clock enable input.

The AS7C33512NTD18A operates with a 3.3V ± 5% power supply for the device core (V_DD). DQ circuits use a separate power supply (V_DDQ) that operates across 3.3V or 2.5V ranges. These devices are available in a 100-pin 14×20 mm TQFP package.