AS7C33512FT18A

The AS7C33512FT18A is a high-performance CMOS 16-Mbit synchronous Static Random Access Memory (SRAM) device organized as 524,288 words x 18.

Fast cycle times of 8.5/10/12 ns with clock access times (t_CD) of 7.5/8.5/10.0 ns. Three chip of AS7C33512FT18A enable (CE) inputs permit easy memory expansion. Burst operation of AS7C33512FT18A  is initiated in one of two ways: the controller address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses.

Read cycles of AS7C33512FT18A are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register when ADSP is sampled LOW, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation, the data of AS7C33512FT18A accessed by the current address registered in the address registers by the positive edge of CLK are carried to the data-out buffer. ADV is ignored on the clock edge that samples ADSP asserted, but AS7C33512FT18A is sampled on all subsequent clock edges. Address of AS7C33512FT18A is incremented internally for the next access of the burst when ADV is sampled LOW and both address strobes are HIGH. Burst mode is selectable with the LBO input. With LBO unconnected or driven HIGH, burst operations use an interleaved count sequence. With LBO driven LOW, the device uses a linear count sequence.

Write cycles of AS7C33512FT18A are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 32/ 36 regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is HIGH, one or more bytes may be written by asserting BWE and the appropriate individual byte BWn signals. 

BWn is ignored on the clock edge that samples ADSP LOW, but AS7C33512FT18A is sampled on all subsequent clock edges. Output buffers are disabled when BWn is sampled LOW regardless of OE. Data is clocked into the data input register when BWn is sampled LOW. Address is incremented internally to the next burst address if BWn and ADV are sampled LOW.

Read or write cycles may also be initiated with ADSC instead of ADSP. The differences of AS7C33512FT18Abetween cycles initiated with ADSC and ADSP are as follows:
      • ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.
      • WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP HIGH).
      • Master chip enable CE0 blocks ADSP, but not ADSC.

The AS7C33512FT18A family operates from a core 3.3V power supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V. These devices are available in 100-pin TQFP.