AS7C332MFT18A

• Fast clock to data access: 7.5/8.5/10 ns
• Fast OE access time: 3.5/4.0 ns
• Fully synchronous flow-through operation
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Individual byte write and global write
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V_DDQ
• Linear or interleaved burst control
• Snooze mode for reduced power-standby
• Common data inputs and data outputs

The AS7C332MFT18A is a high-performance CMOS 32-Mbit synchronous Static Random Access Memory (SRAM) device organized as 2,097152 words × 18 bits.

Fast cycle times of 8.5/10/12 ns with clock access times (tCD) of 7.5/8.5/10 ns. Three chip of AS7C332MFT18A enable (CE) inputs permit easy memory expansion. Burst operation of AS7C332MFT18A is initiated in one of two ways: the controller address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses.

Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register when ADSP is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation, the data of AS7C332MFT18A  accessed by the current address registered in the address registers by the positive edge of CLK are carried to the data-out buffer. ADV is ignored on the clock edge that samples ADSP asserted, but AS7C332MFT18A is sampled on all subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled low and both address strobes are high. Burst mode of AS7C332MFT18A  is selectable with the LBO input. With LBO unconnected or driven high, burst operations use an interleaved count sequence. With LBO driven low, the device uses a linear count sequence.

Write cycles of AS7C332MFT18A are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 18 bits regardless of the state of individual BW[a,b] inputs. Alternately, when GWE is high, one or more bytes of AS7C332MFT18A may be written by asserting BWE and the appropriate individual byte BWn signals.

BWn is ignored on the clock edge that samples ADSP low, but AS7C332MFT18A is sampled on all subsequent clock edges. Output buffers are disabled when BWn is sampled LOW regardless of OE. Data is clocked into the data input register when BWn is sampled low. Address of AS7C332MFT18A is incremented internally to the next burst address if BWn and ADV are sampled low.

Read or write cycles may also be initiated with ADSC instead of ADSP. The differences of AS7C332MFT18A between cycles initiated with ADSC and ADSP follow.