AS7C331MNTD36A

The AS7C331MFT18A is a high-performance CMOS 16-Mbit synchronous Static Random Access Memory (SRAM) device organized as 1,048,576 words x18 bits.

Fast cycle times of 7.5/8.5/10/12 ns with clock access times (tCD) of 6.8/7.5/8.5/10 ns. Three chip enable (CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV)of AS7C331MNTD36A allows subsequent internally generated burst addresses.

Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register when ADSP is sampled LOW, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation, the data of AS7C331MNTD36A accessed by the current address registered in the address registers by the positive edge of CLK is carried to the data-out buffers. ADV is ignored on the clock edge that samples ADSP asserted, but AS7C331MNTD36A is sampled on all subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled LOW and both address strobes are HIGH. Burst mode is selectable with the LBO input. With LBO unconnected or driven HIGH, burst operations use an interleaved count sequence. With LBO driven LOW, the device uses a linear count sequence.

Write cycles of AS7C331MNTD36A are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 18 bits regardless of the state of individual BW[a,b] inputs. Alternately, when GWE is HIGH, one or more bytes may be written by asserting BWE and the appropriate individual byte BWn signals.

BWn AS7C331MNTD36A is ignored on the clock edge that samples ADSP LOW, but AS7C331MNTD36A is sampled on all subsequent clock edges. Output buffers are disabled when BWn is sampled LOW, regardless of OE. Data is clocked into the data input register when BWn is sampled LOW. Address is incremented internally to the next burst address if BWn and ADV are sampled LOW.