AS7C33128PFS36A

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect reliability.

The AS7C33128PFS32A and AS7C33128PFS36A are high-performance CMOS 4-Mbit synchronous Static Random Access Memory (SRAM) devices organized as 131,072 words × 32 or 36 bits, and incorporate a two-stage register-register pipeline for highest frequency on any given technology.

Timing for AS7C33128PFS36A is compatible with existing Pentium® synchronous cache specifications. This architecture is suited for ASIC, DSP (TMS320C6X), and PowerPC™1-based systems in computing, datacom, instrumentation, and telecommunications systems.

Fast cycle times of 5.0/5.4/6.0/7.5/10 ns with clock access times (t_CD) of 3.0/3.1/3.5/4.0/5.0 ns enable 200, 183, 166, 133 and 100 MHz bus frequencies. Two-chipe (CE) inputs permit easy memory expansion. Burst operation of AS7C33128PFS36A is initiated in one of two ways: the controller address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses.

Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register when ADSP is sampled low, the chip enables are sampled active, and the output buffer of AS7C33128PFS36A is enabled with OE. In a read operation, the data accessed by the current address registered in the address registers by the positive edge of CLK are carried to the data-out registers and driven on the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted, but AS7C33128PFS36A is sampled on all subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled low and both address strobes are high. Burst mode is selectable with theLBOinput. With LBO unconnected or driven high, burst operations use an interleaved count sequence. WithLBOdriven low, AS7C33128PFS36A uses a linear count sequence.

Write cycles of AS7C33128PFS36A are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 18 bits regardless of the state of individual BW[a,b]inputs. Alternately, when GWE is high, one or more bytes may be written by asserting BWE and the appropriate individual byte BWn signals.

BWn is ignored on the clock edge that samples ADSP low, but AS7C33128PFS36A is sampled on all subsequent clock edges. Output buffers are disabled when BWnis sampled LOW regardless of OE. Data is clocked into the data input register when BWn is sampled low. Address is incremented internally to the next burst address if BWn and ADV are sampled low. AS7C33128PFS36A operates in doublecycle deselect feature during read cycles.

Read or write cycles may also be initiated with ADSC instead of ADSP. The differences of AS7C33128PFS36A between cycles initiated withADSCand ADSP are as follows:
• ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
•WE signals are sampled on the clock edge that samples ADSClow (and ADSP high).
•Master chip enable CE0 blocks ADSP, but not ADSC.

AS7C33128PFS32A and AS7C33128PFS36A family operates from a core 3.3V power supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V. These devices are available in a 100-pin 14 × 20 mm TQFP package.