AS7C33128NTD18B-166TQC

The AS7C33128NTD18B-166TQC is a high performance CMOS 2 Mbit synchronous static random access memory (SRAM) organized as 131,072 words × 18 bits and incorporates a LATE LATE write.The AS7C33128NTD18B-166TQC operates with a 3.3V ± 5% power supply for the device core (VDD).DQ circuits use a separate power supply (VDDQ) that operates across 3.3V or 2.5V ranges. These devices are available in a 100-pin 14×20 mm TQFP package.
 
Features of the AS7C33128NTD18B-166TQC are:(1)organization: 131,072 words × 18 bits;(2)fast clock to data access: 3.0/3.5/4.0 ns;(3)fast OE access time: 3.0/3.5/4.0 ns;(4)fully synchronous flow-through operation;(5)asynchronous output enable control;(6)available in 100-pin TQFP package;(7)byte write enables;(8)multiple chip enables for easy expansion;(9)3.3V core power supply;(10)2.5V or 3.3V I/O operation with separate VDDQ;(11)self-timed write cycles;(12)interleaved or linear burst modes;(13)NTD™ architecture for efficient bus operation;(14)fast clock speeds to 200 MHz;(15)clock enable for operation hold;(16)snooze mode for standby operation.

The recommended operating conditions of the AS7C33128NTD18B-166TQC can be summarized as:(1):the parameter is supply voltage for inputs,the symbol is VDD,the Min is 3.135,the Nominal is 3.3,the Max is 3.465,the unit is V;(2):the parameter is supply voltage for I/O,the symbol is VDDQ,the Min is 3.135,the Nominal is 3.3,the Max is VDD,the unit is V;(3):the parameter is ground supply,the symbol is VDD,the Min is 0,the Nominal is 0,the Max is 0,the unit is V.