AS7C33128FT36B

The AS7C33128FT32B/36B is a high-performance CMOS 4-Mbit synchronous Static Random Access Memory (SRAM device organized as 131,072 words × 32 or 36 bits.

Fast cycle times of 7.5/8.5/10/12 ns with clock access times (tCD) of 6.5/7.5/8.0/10 ns. Three chip enable (CE ) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC ), or the processor address strobe (ADSP ). The burst advance pin (ADV ) allows subsequent internally generated burst addresses.

Read cycles are initiated with ADSP (regardless of WE and ADSC ) using the new external address clocked into the on chip address register when ADSP is sampled low, the chip enables are sampled active, and the output buffer is enabled with CE . In a read operation, the data accessed by the current address registered  in the address registers by the positive edge of CLK are carried to the data-out buffer. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on all subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled low and both address strobes are high. Burst mode is selectable with the LBO input. With LBO unconnected or driven high, burst operations use an interleaved count sequence. With LBO driven low, the device uses a linear count sequence.