AS7C33128FT32B-10TQCN

The AS7C33128FT32B-10TQCN is one member of the AS7C33128FT32B series.The AS7C33128FT32B is a high-performance CMOS 4-Mbit synchronous Static Random Access Memory (SRAM) device organized as 131,072 words * 32 or 36 bits.Fast cycle times of 7.5/8.5/10/12 ns with clock access times (tcd ) of 6.5/7.5/8.0/10 ns. Three chip enable (CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe(ADSC), or the processor address strobe (ADSP).The burst advance pin (ADV) allows subsequent internally generated burst addresses.

Features of the AS7C33128FT32B-10TQCN are:(1)fast OE access time: 3.5/4.0 ns; (2)fully synchronous flow through operation; (3)asynchronous output enable control; (4)available in 100-pin TQFP package; (5)individual byte write and global write; (6)multiple chip enables for easy expansion; (7)3.3V core power supply; (8)2.5V or 3.3V I/O operation with separate VDDQ; (9)linear or interleaved burst control;(10)snooze mode for reduced power standby; (11)common data inputs and data outputs.

The absolute maximum ratings of the AS7C33128FT32B-10TQCN can be summarized as:(1)power supply voltage relative to GND:-0.5V to 4.6V;(2)input voltage relative to GND:-0.5V to Vdd+0.5V;(3)storage temperature:-65 to 150;(4)temperature under bias:-65 to 135;(5)power dissipation:1.8W.Stresses greater than those listed under "Absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect reliability. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document.The data contained herein represents Alliance's best data and/or estimates at the time of issuance.