AS7C33128FT18B

• Organization: 131,072 words × 18 bits
• Fast clock to data access: 6.5/7.5/8.0/10.0 ns
• Fast OE access time: 3.5/4.0 ns
• Fully synchronous flow through operation
• Asynchronous output enable control
• Economical 100-pin TQFP package
• Individual byte write and Global write
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate VDDQ
• Linear or interleaved burst control
• Snooze mode for reduced power standby
• Common data inputs and data outputs

The AS7C33128FT18B is a high-performance CMOS 2-Mbit synchronous Static Random Access Memory (SRAM) device organized as 131,072 words × 18 bits.

Fast cycle times of 7.5/8.5/10/12 ns with clock access times (tCD) of 6.5/7.5/8.0/10 ns. Three chip of AS7C33128FT18Benable ( CE ) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe ( ADSC ), or the processor address strobe ( ADSP ).

The burst advance pin ( ADV )of AS7C33128FT18B  allows subsequent internally generated burst addresses.

Read cycles AS7C33128FT18B are initiated with ADSP (regardless of WE and ADSC ) using the new external address  clocked into the on chip address register when ADSP is sampled low, the chip of AS7C33128FT18B enables are sampled active, and the output buffer is enabled with OE. In a read operation, the data accessed by the current address registered in the address registers by the positive edge of CLK are carried to the data-out buffer. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on all subsequent clock edges. Address of AS7C33128FT18B is incremented internally for the next access of the burst when ADV is sampled low and both address strobes are high. Burst mode is selectable with the LBO input. With LEO unconnected or driven high, burst operations of  AS7C33128FT18B use an interleaved count sequence. With LBO driven low, the device uses a linear count sequence.