AS7C33128FT18B-10TQCN

The AS7C33128FT18B-10TQCN is one member of the MX29F022N series.The AS7C33128FT18B is a high-performance CMOS 2-Mbit synchronous Static Random Access Memory (SRAM) device organized as 131,072 words * 18 bits.Fast cycle times of 7.5/8.5/10/12 ns with clock access times (t CD) of 6.5/7.5/8.0/10 ns. Three chip enable (CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the processor address strobe (ADSP).The burst advance pin (ADV) allows subsequent internally generated burst addresses.

Features of the AS7C33128FT18B-10TQCN are:(1)fully synchronous flow through operation; (2)asynchronous output enable control; (3)economical 100-pin TQFP package; (4)individual byte write and global write; (5)multiple chip enables for easy expansion; (6)3.3V core power supply; (7)2.5V or 3.3V I/O operation with separate VDDQ; (8)linear or interleaved burst control; (9)snooze mode for reduced power standby; (10)common data inputs and data outputs.

The absolute maximum ratings of the AS7C33128FT18B-10TQCN can be summarized as:(1)power supply voltage relative to GND:-0.5V to 4.6V;(2)input voltage relative to GND:-0.5V to Vdd+0.5V;(3)storage temperature:-65 to 150;(4)temperature under bias:-65 to 135;(5)power dissipation:1.8W.All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document.The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible.

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