Features: •Industrial and commercial versions
•Organization: 65,536 words * 16 bits
•Center power and ground pins for low noise
•High speed
-10/12/15/20 ns address access time
-5, 6, 7, 8 ns output enable access time
•Low power consumption: ACTIVE
-288 mW / max @ 10 ns
•Low power consumption: STANDBY
-18 mW / max CMOS I/O
•6 T 0.18 u CMOS technology
•Easy memory expansion with CE, OE inputs
•TTL-compatible, three-state I/O
•JEDEC standard packaging
-44-pin 400 mil SOJ
-44-pin TSOP 2-400
•ESD protection 2000 volts
•Latch-up current 200 mA
Pinout
Specifications
Parameter
|
Symbol
|
Min
|
Max
|
Unit |
Voltage on VCC
relative to GND
|
Vt1 |
0.50 |
+5.0 |
V |
Voltage on any pin relative to GND
|
Vt2
|
0.50
|
VCC+0.50 |
V |
Power dissipation
|
PD
|
|
1.0 |
W |
Storage temperature (plastic)
|
Tstg
|
65 |
+150
|
|
Ambient temperature
with VCC applied
|
Tbias
|
55 |
+125
|
|
DC current into outputs (low)
|
IOUT
|
|
20mA |
mA |
DescriptionThe AS7C31026B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 65,536 words× 16 bits. It is designed for memory applications where fast data access, low power, and si mple interfacing are desired.Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns are ideal forhigh-performance applications.When CEis high, the device enters standby mode.
A write cycle of AS7C31026B-10TC is accomplished by asserting write enable (WE) and chip enable (CE). Dataon the input pins I/O0 through I/O15 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention,external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).A read cycle is accomplished by asserting output enable (OE) and chip enable (CE) with write enable (WE) high. The AS7C31026B-10TC drive I/O pinswith the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output drivers stay in hi gh-impedance mode.
AS7C31026B-10TC provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written andread.LB controls the lower bits, I/O0 through I/O7, and BU controls the higher bits, I/O8 through I/O15. All chip inputs and outputs are TTL-compatible, and operation is from asingle 3.3 V supply. AS7C31026B-10TC is packaged in common industrystandard packages.
AS7C31026B-10TC Data Sheet
