Features: •Industrial and commercial temperatures
•Organization: 131,072 words x 8 bits
•High speed
-10/12/15/20 ns address access time
-5, 6, 7, 8 ns output enable access time
•Low power consumption: ACTIVE
-252 mW / max @ 10 ns
•Low power consumption: STANDBY
-18 mW / max CMOS
•6T 0.18u CMOS technology
•Easy memory expansion with CE1</a>, CE2</a>, OE inputs
•TTL/LVTTL-compatible, three-state I/O
•32-pin JEDEC standard packages
-300 mil SOJ
-400 mil SOJ
-8 * 20mm TSOP 1
-8 x 13.4mm s TSOP 1
•ESD protection 2000 volts
•Latch-up current 200 mAPinout
Specifications
| Parameter |
Symbol |
Min |
Max |
Unit |
| Voltage on VCC relative to GND |
Vt1 |
-0.50 |
+5.0 |
V |
| Voltage on any pin relative to GND |
Vt2 |
0.50 |
VCC +0.50 |
V |
| Power dissipation |
PD |
|
1.0 |
W |
| Storage temperature (plastic) |
Tstg |
65 |
+150 |
°C |
| Ambient temperature with VCC applied |
Tbias |
55 |
+125 |
°C |
| DC current into outputs (low) |
IOUT |
|
20 |
mA |
DescriptionThe AS7C31024B is a high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 131,072 words x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access of AS7C31024B and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns are ideal for high performance applic ations. Active high and low chip enables (CE1</a>, CE2) permit easy memory expansion with multiple-bank systems.
When CE1</a> is high or CE2 is low, the device enters standby mode. If inputs are still toggling, AS7C31024B will consume ISB power. If the bus is static, then full standby power is reached (ISB1). For example, the AS7C31024B is guaranteed not to exceed 18mW under nominal fullstandby conditions.
A write cycle of AS7C31024B is accomplished by asserting write enable (WE</a>) and both chip enables (CE1</a>, CE2). Data on the input pins I/O0 through I/O7 is written on the rising edge of WE</a> (write cycle 1) or the active-to-inactive edge of CE1</a> or CE2 (write cycle 2). To avoid bus contention,external devices should drive I/O pins only after outputs have been disabled with output enable (OE</a>) or write enable (WE</a>).
A read cycle of AS7C31024B is accomplished by asserting output enable (OE</a>) and both chip enables (CE1</a>, CE2), with write enable (WE</a>) high. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode.
AS7C31024B Data Sheet
