Features: •Pin compatible with AS7C256
•Industrial and commercial temperature options
•Organization: 32,768 words * 8 bits
•High speed
-10/12/15/20 ns address access time
-5, 6, 7, 8 ns output enable access time
•Very low power consumption: ACTIVE
-412.5 mW max @ 10 ns
•Very low power consumption: STANDBY
-11 mW max CMOS I/O
•Easy memory expansion with CE</a> and OE</a> inputs
•TTL-compatible, three-state I/O
•28-pin JEDEC standard packages
-300 mil SOJ
-8 * 13.4 mm TSOP 1
•ESD protection 2000 volts
•Latch-up current 200 mA
•2.0V Data retentionPinout
Specifications
| Parameter |
Symbol |
Min |
Max |
Unit |
| Voltage on VCC relative to GND |
Vt1 |
-0.5 |
+7.0 |
V |
| Voltage on any pin relative to GND |
Vt2 |
0.5 |
VCC +0.5 |
V |
| Power dissipation |
PD |
|
1.0 |
W |
| Storage temperature (plastic) |
Tstg |
65 |
+150 |
°C |
| Ambient temperature with VCC applied |
Tbias |
55 |
+125 |
°C |
| DC current into outputs (low) |
IOUT |
|
20 |
mA |
DescriptionThe AS7C256A is a 5.0V high-performance CMOS 262,144-bit Static Random-Access Memory (SRAM) device organized as 32,768 words * 8 bits. It is designed for memory applications requiring fast data access at low voltage, including PentiumTM, PowerPCTM, and portable computing. Alliance's advanced circuit design and process techniques permit 5.0V operation without sacrificing performance or operating margins.
AS7C256A enters standby mode when CE</a> is high. CMOS standby mode consumes 11 mW. Normal operation offers 75% power reduction after initial access, resulting in significant power savings during CPU idle, suspend, and stretch mode.
Equal address access of AS7C256A and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns are ideal for high-performance applications. The chip enable (CE</a>) input permits easy memory expansion with multiple-bank memory organizations.
A write cycle of AS7C256A is accomplished by asserting chip enable (CE</a>) and write enable (WE</a>) LOW. Data on the input pins I/O0-I/O7is written on the rising edge of WE</a> (write cycle 1) or CE</a> (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE</a>) or write enable (WE</a>).
A read cycle of AS7C256A is accomplished by asserting chip enable (CE</a>) and output enable (OE</a>) LOW, with write enable (WE</a>) high. The chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write enable is low, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible. Operation is from a single 5.0 ±0.5V supply. The AS7C256A is packaged in high volume industry standard packages.
AS7C256A Data Sheet
