AS7C256A-10JI

The AS7C256A is a 3.3V high-performance CMOS 262,144-bit Static Random-Access Memory (SRAM) device organized as 32,768 words * 8 bits. AS7C256A-10JI is designed for memory applications re quiring fast data access at low voltage, including Pentium^TM, PowerPC^TM, and portable computing. A lliance's advanced circuit design and process techniques permit 3.3V operation without sacrificing performance or operating margins.

AS7C256A-10JI enters standby mode when CE  is high. CMOS standby mode consumes 7.2 mW.  Normal operation offers 75% power reduction after initial access, resulting in significant power savings during CPU idle, suspend, and stretch mode.

Equal address access of AS7C256A-10JI and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (t OE ) of 5, 6, 7, 8 ns are ideal for high-performance applications. The chip enable (CE  input permits easy memory expansion with multiple-bankmemory organizations.

A write cycle of AS7C256A-10JI is accomplished by assertingchip enable (CE  and write enable (WE ) LOW. Data on the input pins I/O0-I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE ) or write enable WE).

A read cycle of AS7C256A-10JIis accomplished by asserting chip enable (CE ) and output enable (OE ) LOW, with write enable WE  high. The chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write enable is low, output drivers stay in high-impedance mode.All chip inputs and outputs are TTL-compatible. Operation of AS7C256A-10JI is from a single 3.3 ±0.3V supply. The AS7C3256A is packaged in high volume industry standard packages.