Features: • Organization: 1,048,576 words × 32 or 36 bits
• NTD™architecture for efficient bus operation
• Fast clock speeds to 200 MHz
• Fast clock to data access: 3.2/3.5/3.8 ns
• Fast OE access time: 3.2/3.5/3.8 ns
• Fully synchronous operation
• pipelined mode
• Common data inputs and data outputs
• Asynchronous output enable control
• Available in 100-pin TQFP packages
• Byte write enables
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 2.5V core power supply
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operationPinout
Specifications
| Parameter |
Symbol |
Min |
Max |
Unit |
| Power supply voltage relative to GND VDD, |
VDD,VDDQ |
0.3 |
+3.6 |
V |
| Input voltage relative to GND (input pins) |
VIN |
0.3 |
VDD + 0.3 |
IV |
| Input voltage relative to GND (I/O pins) |
VIN |
0.3 |
VDDQ + 0.3 |
V |
| Power dissipation |
PD |
|
1.8 |
W |
| DC output current |
IOUT |
|
50 |
mA |
| Storage temperature |
Storage temperature Tstg |
65 |
+150 |
oC |
| Temperature under bias (junction) |
Temperature under bias (junction) Tbias |
65 |
+125 |
oC |
DescriptionThe AS7C251MNTD32A/36A family is a high performance CMOS 32 Mbit synchronous Static Random Access Memory (SRAM)organized as 1,048,576 words × 32 or 36 bits and incorporates a LATE LATE Write.
This variation of the 32Mb+ synchronous SRAM uses the No Turnaround Delay (NTD. architecture, featuring an enhanced write operation that improves bandwidth over pipelined burst devices. In a normal pipelined burst device, the write data, command, and address are all applied to the device on the same clock edge. If a read command follows this write command, the system must wait for two 'dead' cycles for valid data to become available. These dead cycles can significantly reduce overall bandwidth for applications requiring random access or read-modify-write operations.
NTD. devices use the memory bus more efficiently by introducing a write latency which matches the two-cycle pipelined or one-cycle flow-through read latency. Write data is applied two cycles after the write command and address, allowing the read pipeline to clear. With NTD., write and read operations can be used in any order without producing dead bus cycles.
Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 32/36 bit writes. Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied to the device two clock cycles later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write operations; it can be tied low for
normal operations. Outputs go to a high impedance state when the device is de selected by any of the three chip enable inputs. In pipelined mode, a two cycle deselect latency allows pending read or write operations to be completed.
Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is high, external addresses, chip select, R/W pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any device operations, including burst, can be stalled using the CEN=1, the clock enable input.
The AS7C251MNTD32A/36A operates with a 2.5V ± 5% power supply for the device core (VDD). These devices are available in a 100-pin TQFP package.
AS7C251MNTD32A Data Sheet
