Features: ` Industrial and commercial temperatures
`Organization: 65,536 words x 16 bits
` High speed
- 10/12/15/20 ns address access time
- 5/6/7/8 ns output enable access time
`Low power consumption: ACTIVE
- 605 mW / max @ 10 ns
` Low power consumption: STANDBY
- 55 mW / max CMOS
` 6T 0.18u CMOS technology
` Easy memory expansion withCE , OE inputs
` TTL/LVTTL-compatible, three-state I/O
`JEDEC standard packaging
- 44-pin 400 mil SOJ
- 44-pin TSOP 2-400
` ESD protection 2000 volts
`Latch-up current 200 mA
Specifications
| Parameter |
Symbol |
Min |
Max |
Unit |
| Voltage on VCC relative to GND |
Vt1 |
-0.50 |
+70 |
V |
| Voltage on any I/O pin relative to GND |
Vt2 |
0.50 |
VCC+ 0.50 |
V |
| Power dissipation |
PD |
|
1.0 |
W |
| Storage temperature (plastic) |
Tstg |
65 |
+150 |
|
Temperature with VCC applied
|
Tbias |
55 |
+125 |
|
| DC output current (low) |
IOUT |
|
20 |
mA |
Description
The AS7C1026B is a high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 65,536 words x 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA , t RC , tWC ) of 10/12/15/20 ns with output enable access times (tOE ) of 5/6/7/8 ns are ideal for high performance applications.
When CE is high the devices enter standby mode. If inputs are still toggling, the device will consume I power. If the bus is SB static, then full standby power is reached (ISB1 ). For example, the AS7C1026B is guaranteed not to exceed 55mW under nominal full standby conditions.
A write cycle is accomplished by asserting write enable (WE ) and both chip enables (CE ). Data on the input pins I/O0 through I/O15 is written on the rising edge of WE or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE ).
A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE ), with write enable (WE ) high. The chips drive I/O pins with the data word referenced by the input address. When either chip enable is inactive, output enable is inactive, or write enable is active,output drivers stay in high-impedance mode.
The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O0 through I/O7, and UB controls the higher bits, I/O8 through I/O15.
All chip inputs and outputs are TTL-compatible, and operation is from a single 5 V supply. The device is packaged in common industry standard packages.
AS7C1026B-12TI Data Sheet
