ACT-F128K8

Note 1. Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, inputs may undershoot VCC + 0.5V. During voltage transitions, inputs and I/O pins may up to 20ns. Maximum DC voltage on input and I/O pins is VCC + 2.0V for periods up to 20 ns.overshoot to VSS to -2.0v for periods of
Note 2. Minimum DC input voltage on A9 is -0.5V. During voltage transitions, A9 may undershoot VSS to -2.0V for periods of up to 20ns.
Maximum DC input voltage on A9 is +12.5V which may overshoot to 14.0V for periods up to 20ns. 

The ACT - F128K8 is a hig speed, 1 megabit CMOS monolithic Flash module designed for full temperature range military, space, or high reliability applications.

This device ACT-F128K8 is input TTL and output CMOS compatible. The command register is written by ) and bringing write enable (WE) to a logic low chip enable (CE) to alevel and output enable (OE logic high level. Reading is is high accomplished when WE , OE are both low, see and CE Figure 9. Access time grades of 60ns, 70ns, 90ns, 120ns and 150ns maximum are standard.

The ACT¨CF128K8 iavailable  in a  choice of hermetically sealed ceramic packages; a 32 lead  .82" x .41" x .125" flat package in both formed or unformed leads or a 32 pin 1.6"x.60" x.20" DIP package for operation over  the temperature range  -55 to +125 and military environmenta conditions.

The flash memory of ACT-F128K8 is organized as 128Kx8  bits and is designed to be programmed in-system with the standard PP is system 5.0V Vcc supply.  A 12.0V V not required for write or erase operations.

The device ACT-F128K8 can also be reprogrammed with standard EPROM programmers (with the proper socket).

The standard ACT¨CF128K8 offer access times between 60ns and 150ns, allowing operation of high-speed microprocessors without wait states.  To eliminate bus contention, the device has ), write enable separate chip enable (CE) and output enable (OE) controls.  The (WE ACT - F128K8 is command set compatibl with JEDEC standard 1 Mbit EEPROMs.

Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations.

Reading data out of the device ACT-F128K8 is similar to reading from 12.0V Flash or EPROM devices. The ACT¨CF128K8 is programme by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Typically, each sector can be programmed and verified in less than 0.3 second. Erase is accomplished by executing the erase command sequence.

This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array, (if it is not already programmed before) executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.

Also the device ACT-F128K8 features a sector erase architecture. The sector mode allows for 16K byte blocks of memory to be erased and reprogrammed without affecting other blocks. The ACT-F128K8 is erased when shipped from the factory.
The device features single 5.0V power supply operation for both read and write functions. lnternally generated and regulated voltages are provided for the program and erase operations. A low V CC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by  Data Polling of D7 or by the Toggle Bit feature on D6. Once the end of a program or erase cycle has been completed, the device internally resets to the read mode.

 All bits of each die, or all bits within a sector of a die, are erased via Fowler-Nordhiem tunneling. Bytes are programmed one byte at a time by hot electron injection.

A DESC Standard Military Drawing (SMD) number is pending.