A49LF040A

The A49LF040A flash memory device is designed to be read-compatible with the Intel Low Pin Count (LPC) Interface Specification 1.1. This device is designed to use a single low voltage, range from 3.0 Volt to 3.6 Volt power supply to perform in-system or off-system read and write operations. It provides protection for the storage and update of code and data in addition to adding system design flexibility through five general-purpose inputs. Two interface modes are supported by the A49LF040A: Low Pin Count (LPC) Interface mode for In-System programming and Address/Address Multiplexed (A/A Mux) mode for fast factory programming of PC-BIOS applications.

The memory is divided into eight uniform 64Kbyte blocks that can be erased independently without affecting the data in other blocks. Blocks also can be protected individually to prevent accidental Program or Erase commands from modifying the memory. The boot block can be write protected by a hardware method controlled by the TBL pin or a register-based protection turned on/off by the Block Locking Registers (LPC mode only). The rest of blocks except boot block in the device also can be write protected by WP pin or
Block Locking Registers (LPC mode only). The Program and Erase operations are executed by issuing the Program/Erase commands into the command interface by which activating
the internal control logic to automatically process the Program/Erase procedures. The device can be programmed on a byte-by-byte basis after performing the Erase operation.

In addition to the Block Erase operation, the Chip Erase feature is provided in A/A Mux mode that allows the whole memory to be erased in one single Erase operation. The A49LF040A provides the status detection such as Data Polling (I/O7) and Toggle Bit (I/O6) Functions in both FWH/LPC and A/A Mux modes. The process or completion of Program and Erase operations can be detected by reading the status bits.

The A49LF040A is offered in 32-lead TSOP and 32-lead PLCC packages with optional environmental friendly leadfree package. See Figures 1 and 2 for pin assignments and Table 1 for pin descriptions.