A49LF004

Temperature Under Bias . . . . . . . .  . .  -55°C to + 125°C
Storage Temperature . . . . . . . . . . . . . -65°C to + 125°C
D.C. Voltage on Any Pins with Respect to Ground (1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to V_DD + 0.5V
Package Power Dissipation Capability (Ta=25°C)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to V_DD + 0.5V
Output Short Circuit Current (2) . . . . . . . . . . . . . . . . 50mA
Notes:
1. Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, input or I/O pins may undershoot VSS to 2.0V for periods of up to 20ns. Maximum DC voltage on input and I/O pins is VDD + 0.5V. During voltage transitions, input or I/O pins may overshoot to VDD + 2.0V for periods up to 20ns.
2. No more than one output is shorted at a time. Duration of the short circuit should not be greater than one second.

The A49LF004 flash memory device is designed to be readcompatible with the Intel 82802 Firmware Hub (FWH) device for PC-BIOS application. This device is designed to use a single low voltage, range from 3.0 Volt to 3.6 Volt power supply to perform in-system or off-system read and write operations. It provides protection for the storage and update of code and data in addition to adding system design flexibility through five general-purpose inputs. Two interface modes are supported by the A49LF004: Firmware Hub (FWH) Interface mode for In-System programming and Address/Address Multiplexed (A/A Mux) mode for fast factory programming of PC-BIOS applications. The memory is divided into eight uniform 64Kbyte blocks that can be erased independently without affecting the data in other blocks.

Blocks also can be protected individually to prevent accidental Program or Erase commands from modifying the memory. The Program and Erase operations are executed by issuing the Program/Erase commands into the command interface by which activating the internal control logic to automatically process the Program/Erase procedures.

The device A49LF004 can be programmed on a byte-bybyte basis after performing the Erase operation. In addition to the Block Erase operation, the Chip Erase feature is provided in A/A Mux mode that allows the whole memory to be erased in one single Erase operation. The A49LF004 provides the status detection such as Data# Polling and Toggle Bit Functions in both FWH and A/A Mux modes.

The process or completion of Program and Erase operations can be detected by reading the status bits. The A49LF004 is offered in 32-lead TSOP and 32-lead PLCC packages. See Figures 1 and 2 for pin assignments and Table 1 for pin descriptions.