74F786

The 74F786 is an asynchronous 4bit arbiter designed for high speed realtime applications. The priority of arbitration is determined on a firstcome firstserved basis. Separate bus grant (BG n) outputs are available to indicate which one of the request inputs is served by the arbitration logic. All BGn outputs are enabled by a common enable (EN) pin. In order to generate a bus request signal a separate 4 input AND gate is provided which may also be used as an independent AND gate. Unused bus request (BR) inputs may be disabled by tying them high.

The 74F786 is designed so that contention between two or more request signals will not glitch or display a metastable condition. In this situation an increase in the BRn to BGn tPHL may be observed. A typical 74F786 has an h = 6.6ns, t = 0.41ns and To = 5msec.

Where:

h = Typical propagation delay through the device and t and To are device parameters derived from test results and can most nearly be defined as:

t = A function of the rate at which a latch in a metastable state resolves that condition.

To = A function of the measurement of the propensity of a latch to enter a metastable state. To is also a very strong function of the normal propagation delay of the device.

For further information, please refer to the 74F786 application notes.