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74F597

Features: • High impedance PNP base inputs for reduced loading (20mA in High and Low states)• 8-bit parallel storage register• 3-State output buffers• Shift register has asynchronous direct overriding reset• Shift load SHLD is functional when SHCP is Low and locked ou...

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SeekIC No. : 004249808 Detail

74F597: Features: • High impedance PNP base inputs for reduced loading (20mA in High and Low states)• 8-bit parallel storage register• 3-State output buffers• Shift register has asyn...

74F597 Data Sheet

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Part Number:
74F597
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/21

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Product Details

Description



Features:

• High impedance PNP base inputs for reduced loading (20mA in High and Low states)
• 8-bit parallel storage register
• 3-State output buffers
• Shift register has asynchronous direct overriding reset
• Shift load SHLD is functional when SHCP is Low and locked out when SHCP is High
• Guaranteed shift frequency DC to 105MHz


Pinout

Connection Diagram


Specifications

SYMBOL PARAMETER RATING UNIT
VCC Supply voltage 0.5 to +7.0 V
VIN Input voltage 0.5 to +7.0 V
IIN Input current 30 to +5 mA
VOUT Voltage applied to output in High output state 0.5 to +VCC V
IOUT Current applied to output in Low output state 40 mA
Tamb Operating free-air temperature range 0 to +70 °C
Tstg Storage temperature range 65 to +150 °C



Description

The 74F597 consists of an 8-bit storage register feeding a parallel-in/serial-in, serial-out 8-bit shift register. The storage register and shift register have separate positive edge triggered clocks. The shift register has asynchronous reset and when SHCP is Low, it has asynchronous load.

The shift register load function of the 74F597 has been modified to load when both SHLD and SHCP are Low. When SHCP is High the shift register load operation is not performed. Data will be properly shifted on the rising edge of SHCP when SHLD is High.




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