74F50729

(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.)

The 74F50729 is a dual positive edgetriggered Dtype featuring individual data, clock, set and reset inputs; also true and complementary outputs.

The 74F50729 is designed so that the outputs can never display a metastable state due to setup and hold time violations. If setup time and hold time are violated the propagation delays may be extended beyond the specifications but the outputs will not glitch or display a metastable state. Typical metastability parameters for the 74F50729 are: t @ 135ps and t @  9.8 X 106 sec where t represents a function of the rate at which a latch in a metastable state resolves that condition and To represents a function of the measurement of the propensity of a latch to enter a metastable state.

Set (SDn) and reset (RDn) are asynchronous positiveedge triggered inputs and operate independently of the clock (CPn) input. Data must be stable just one setup time prior to the lowtohigh transition of the clock for guaranteed propagation delays.

Clock triggering of the 74F50729 occurs at a voltage level and is not directly related to the transition time of the positivegoing pulse. Following the hold time interval, data at the Dn input may be changed without affecting the levels of the output.