74F50728

The 74F50728 is a cascaded dual positive edgetriggered Dtype featuring individual data, clock, set and reset inputs; also true and complementary tputs.

Set (SDn) and reset (RDn) are asynchronous active low inputs and operate independently of the clock (CPn) input. They set and reset both flipflops of a cascaded pair simultaneously. Data must be stable just one setup time prior to the lowtohigh transition of the clock for guaranteed propagation delays.

Clock triggering occurs at a voltage level and is not directly related to the transition time of the positivegoing pulse. Following the hold time interval, data  t the Dn input may be changed without affecting the levels of the output. Data entering the 74F50728 requires two clock cycles to arrive at the outputs.

The 74F50728 is designed so that the outputs can never display a metastable state due to setup and hold time violations. If setup time and hold time are violated the propagation delays may be extended beyond the specifications but the outputs will not glitch or display a metastable state. Typical metastability parameters for the 74F50728 are: t  @   135ps and T0  @  9.8 X 106 sec where t represents a function of the rate at which a latch in a metastable state resolves that condition and To represents a fu nction of the measurement of the propensity of a latch to enter a metastable state.