74F552QC

Number of Channels per Chip : 8
Output Type : 3-State
Maximum Operating Temperature : + 70 C
Supply Voltage - Max : 5.5 V
Supply Voltage - Min : 4.5 V
Logic Type : Bipolar
Input Level : TTL
Output Level : TTL
High Level Output Current : - 15 mA
Propagation Delay Time : 9.5 ns
Low Level Output Current : 64 mA
Package / Case : PLCC-28
Packaging : Rail
Logic Family : 74F


Features:

8-Bit bidirectional I/O Port with handshake
Register status flag flip-flops
Separate clock enable and output enable
Parity generation and parity check
B-outputs sink 64 mA
3-STATE outputs


Pinout




Specifications

Storage Temperature..................... -65°C to +150°C
Ambient Temperature under Bias... -55°C to +125°C
Junction Temperature under Bias... -55°C to +175°C
V_CC Pin Potential to Ground Pin .........-0.5V to +7.0V
Input Voltage (Note 2)....................... -0.5V to +7.0V
Input Current (Note 2) .................-30 mA to +5.0 mA
Voltage Applied to Output
    in HIGH State (with V_CC = 0V)
    Standard Output ...............................-0.5V to V_CC
    3-STATE Output ..............................-0.5V to +5.5V
Current Applied to Output
    in LOW State (Max) .........twice the rated I_OL (mA)
ESD Last Passing Voltage (Min)....................... 4000V
Free Air Ambient Temperature.............. 0°C to +70°C
Supply Voltage................................... +4.5V to +5.5V
Note 1:  Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.


Description

The 74F552QC octal transceiver contains two 8-bit registers for temporary storage of data flowing in either direction. Each register has its own clock pulse and clock enable input as well as a flag flip-flop that is set automatically as the register is loaded. The flag output will be reset when the output enable returns to HIGH after reading the output port. Each register of the 74F552QC has a separate output enable control for its 3-STATE buffer. The separate Clocks, Flags, and Enables provide considerable flexibility as I/O ports for demand-response data transfer. When data is transferred from the A Port to the B Port, a parity bit is generated. On the other hand, when data is transferred from the B Port to the A Port, the parity of input data on B₀B₇ is checked.