74F552

Features:

• 8-bit bidirectional I/O port with handshake
• Register status flag flip-flops
• Separate clock enable and output enable
• Parity generation and parity check
• B outputs and parity output sink 64mA


Pinout




Specifications

SYMBOL	PARAMETER		RATING	UNIT
VCC	Supply voltage		0.5 to +7.0	V
VIN	Input current		0.5 to +7.0	V
VIN	Input current		30 to +VCC	mA
VOUT	Voltage applied to output in High output state		0.5 to +VCC	V
IOUT	Current applied to output in Low output state	FR, FS, ERROR	40	mA
		A0A7	48	mA
		B0B7, PARITY	128	mA
Tamb	Operating free-air temperature range		0 to +70	°C
Tstg	Storage temperature		65 to +150	°C

Description

The 74F552 Octal Registered Transceiver contains two 8-bit registers for temporary storage of data flowing in either direction. Each register has its own clock (CPR,CPS) and Clock Enable (CER , CES ) inputs, as well as a flag flip-flop that is set automatically as the register is loaded. The flag output will be reset when the Output Enable returns to High after reading the output port. Each register of the 74F552 has a separate Output Enable (OEAS , OEBR ) for its 3-State buffer. The separate Clocks, Flags and Enables provide considerable flexibility as I/O ports for demand-response data transfer. When data is transferred from the A port to the B port, a parity bit is generated. On the other hand, when data is transferred from the B port to the A port, the parity of input data on B0B7 is checked.