74F524

The 74F524 is an 8-bit bidirectional register with parallel input and output plus serial input and output progressing from LSB to MSB. All data inputs, serial and parallel, are loaded by the rising edge of the input clock. The device functions are controlled by two control lines (S₀ , S₁ ) to exe-cute shift, load, hold and read out.

An 8-bit comparator of the 74F524 examines the data stored in the regis-ters and on the data bus. Three true-HIGH, open-collector outputs representing "register equal to bus", "register greater than bus" and "register less than bus" are provided.These outputs can be disabled to the OFF state by the use of Status Enable (SE ). A mode control has also been pro-vided to allow twos complement as well as magnitude com-pare. Linking inputs of the 74F524 are provided for expansion to longer words.