3D7502

PIN DESCRIPTIONS
RX           Signal Input
CLK         Signal Output (Clock)
DATB       Signal Output (Data)
VCC        +5 Volts
GND        Ground

The 3D7502 product family consists of monolithic CMOS Manchester Decoders. The unit accepts at the RX input a bi-phase-level,embedded-clock signal. In this encoding mode, a logic one is represented by a high-to-low transition within the bit cell, while a logic zero is represented by a low-to-high transition. The recovered clock and data signals are presented on CLK and DATB, respectively, with the data signal inverted. The operating baud rate (in MBaud) is specified by the dash number. The input baud rate may vary by as much as ±15% from the nominal device baud rate without compromising the integrity of the information received.

Because the 3D7502 is not PLL-based, it does not require a long preamble in order to lock onto the received signal. Rather, the device requires at most one bit cell before the data presented at the output is valid. This is extremely useful in cases where the information arrives in bursts and the input is otherwise turned off.