3D7502

Features: · All-silicon, low-power CMOS technology· TTL/CMOS compatible inputs and outputs· Vapor phase, IR and wave solderable· Auto-insertable (DIP pkg.)· Low ground bounce noise· Maximum data rate: 50 MBaud· Data rate range: ±15%Pinout PIN DESCRIPTIONSRX Signal InputCLKSignal Output (Clock)DAT...

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3D7502 Picture
SeekIC No. : 004229777 Detail

3D7502: Features: · All-silicon, low-power CMOS technology· TTL/CMOS compatible inputs and outputs· Vapor phase, IR and wave solderable· Auto-insertable (DIP pkg.)· Low ground bounce noise· Maximum data rat...

floor Price/Ceiling Price

Part Number:
3D7502
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/3/10

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Product Details

Description



Features:

·  All-silicon, low-power CMOS technology
·  TTL/CMOS compatible inputs and outputs
·  Vapor phase, IR and wave solderable
·  Auto-insertable (DIP pkg.)
·  Low ground bounce noise
·  Maximum data rate: 50 MBaud
·  Data rate range: ±15%



Pinout

  Connection Diagram

PIN DESCRIPTIONS
RX           Signal Input
CLK         Signal Output (Clock)
DATB       Signal Output (Data)
VCC        +5 Volts
GND        Ground




Specifications

PARAMETER SYMBOL MIN MAX UNITS NOTES
DC Supply Voltage VDD -0.3 7.0 V  
Input Pin Voltage VIN -0.3 VDD+0.3 V  
Input Pin Current IIN -1.0 1.0 mA 25C
Storage Temperature TSTRG -55 150 C 10 sec
Lead Temperature TLEAD   300 C  



Description

The 3D7502 product family consists of monolithic CMOS Manchester Decoders. The unit accepts at the RX input a bi-phase-level,embedded-clock signal. In this encoding mode, a logic one is represented by a high-to-low transition within the bit cell, while a logic zero is represented by a low-to-high transition. The recovered clock and data signals are presented on CLK and DATB, respectively, with the data signal inverted. The operating baud rate (in MBaud) is specified by the dash number. The input baud rate may vary by as much as ±15% from the nominal device baud rate without compromising the integrity of the information received.

Because the 3D7502 is not PLL-based, it does not require a long preamble in order to lock onto the received signal. Rather, the device requires at most one bit cell before the data presented at the output is valid. This is extremely useful in cases where the information arrives in bursts and the input is otherwise turned off.




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