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XQR17V16VQ44N, XQR17V16VQ44R, XQR18V04

Table of contents:
Info of XQR17V16VQ44N
Info of XQR17V16VQ44R
Info of XQR18V04

XQR17V16VQ44N, XQR17V16VQ44R, XQR18V04 Selling Leads, Datasheet

MFG:XILINX Package Cooled:N/A D/C:09+

XQR17V16VQ44N, XQR17V16VQ44R, XQR18V04 Picture

XQR17V16VQ44N, XQR17V16VQ44R, XQR18V04 Datasheet download

Five Points

Part Number: XQR17V16VQ44N

MFG: XILINX

Package Cooled: N/A

D/C: 09+

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XQR18V04 General Description

Xilinx introduces the QPro™ XQ18V04 and XQR18V04 series of QML in-system programmable and radiation hardened configuration PROMs. Initial devices in this 3.3V family are a 4-megabit PROM that provide an easy-to-use, cost-effective method for re-programming and storing large Xilinx FPGA configuration bitstreams.

When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after the rising CCLK, data is available on the PROM DATA (D0) pin that is connected to the FPGA D_IN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. When the FPGA is in Slave Serial mode, the PROM and the FPGA are clocked by an external clock.

When the FPGA is in Express or SelectMAP Mode, an external oscillator will generate the configuration clock that drives the PROM and the FPGA. After the rising CCLK edge, data are available on the PROMs DATA (D0-D7) pins. The data will be clocked into the FPGA on the following rising edge of the CCLK. Neither Express nor SelectMAP utilize a Length Count, so a free-running oscillator may be used.

XQR18V04 Maximum Ratings

Symbol	Description		Value	Unit
Vcc	Supply voltage relative to GND		0.5 to +4.0	V
V_IN	Input voltage with respect to GND		0.5 to +5.5	V
V_TS	Voltage applied to High-Z output		0.5 to +5.5	V
T_STG	Storage temperature (ambient)		-65 to +150
T_J	Junction Temperature	Ceramic	+150
T_J	Junction Temperature	Plastic	+125

Notes:
1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to 2.0V or overshoot to +7.0V, provided this over- or undershoot lasts less then 10 ns and with the forcing current being limited to 200 mA.

2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

XQR18V04 Features

• In-system programmable 3.3V PROMs for configuration of Xilinx FPGAs
   - Endurance of 2,000 program/erase cycles
   - Program/erase over full military temperature range
• IEEE Std 1149.1 boundary-scan (JTAG) support
• Cascadable for storing longer or multiple bitstreams
• Dual configuration modes
   - Serial Slow/Fast configuration (up to 33 MHz)
   - Parallel (up to 264 Mbps at 33 MHz)
• Low-power advanced CMOS FLASH process
• 5V tolerant I/O pins accept 5V, 3.3V and 2.5V signals.
• 3.3V or 2.5V output capability
• Available in CC44 and VQ44 packages.
• Design support using the Xilinx Alliance™ and Foundation™ series software packages.
• JTAG command initiation of standard FPGA configuration.
• Available to Standard Microcircuit Drawing 5962-01525.
   - For more information contact Defense Supply Center Columbus (DSCC) at http://www.dscc.dla.mil

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