W89C701P, W89C840F, W89C841F Selling Leads, Datasheet
MFG:WINBOND Package Cooled:PLCC D/C:50
W89C701P, W89C840F, W89C841F Datasheet download
Part Number: W89C701P
MFG: WINBOND
Package Cooled: PLCC
D/C: 50
W89C701P, W89C840F, W89C841F
- Table of contents:
Info of W89C701P
Info of W89C840F
Info of W89C841F
Attentive hint
Want to post a buying lead? If you are not a member yet, please select the specific/related part number first and then fill the quantity and your contact details in the "Request for Quotation Form" on the left, and then click "Send RFQ".Your buying lead can then be posted, and the reliable suppliers will quote via our online message system or other channels soon.
Top Sellers:
TOP
About W89C10
PDF/DataSheet Download
Datasheet: W89C10
File Size: 405904 KB
Manufacturer:
Download : Click here to Download
About w89c840f
PDF/DataSheet Download
Datasheet: w89c840f
File Size: 749447 KB
Manufacturer: Winbond
Download : Click here to Download
About W89C841F
PDF/DataSheet Download
Datasheet: W89C841F
File Size: 1182468 KB
Manufacturer: WINBOND [Winbond]
Download : Click here to Download
W89C840F General Description
The W89C840F is a highly integrated Ethernet LAN controller for both 100BaseT and 10BaseT Ethernet. It provides a host bus interface complying with the PCI local bus specification revision 2.1, and the MII interface complying with the IEEE802.3u standard for easily implementing an Ethernet LAN adapter. The built-in 2K bytes transmit FIFO and 4K bytes receive FIFO, controlled by the on-chip bus master, are designed for improving network performance and reducing the host bus utilization.
The on-chip DMA controller handles the data transfer between the host memory and the FIFOs. The data received from network are queued into the receive FIFO and then, directly moved into the host memory through the PCI bus. On the other hand, the transmitted data are fetched from the host memory and directly queued into the transmit FIFO. No extra on-board memory is needed for data buffering during the data transceiving operation.
Many versatile registers, including host bus control registers, direct memory access(DMA) control registers, media access control registers, and signature identification registers, are implemented for system configuring. All of these long words accessible registers perform the status report and the precisely control on the transmit and receive operation. It also provides an extra channel for the on-line application program to update the on-board expansion ROM device in some specific application environment.
W89C840F Maximum Ratings
|
Symbol |
Parameter |
Minimum |
Maximum |
Unit |
|
TA |
Operating Temperature |
0 |
70 |
°C |
|
TS |
Storage Temperature |
-55 |
150 |
°C |
|
VDD |
Supply Voltage |
-0.5 |
7.0 |
V |
|
VIN |
Input Voltage |
VSS-0.5 |
VDD+0.5 |
V |
|
VOUT |
Output Voltage |
VSS-0.5 |
VDD+0.5 |
V |
|
TL |
Lead Temperature (Soldering 10 seconds maximum) |
|
250 |
°C |
W89C840F Features
Complies with IEEE 802.3, 802.3u, ANSI 8802-3 and Ethernet standards
Supports PCI bus master mode for DMA operation, fully complying with PCI 2.1 standard
Early interrupt function available for both transmit and receive
Both half duplex and full duplex available
Independent deep receive and transmit FIFO and no onboard memory required
Flexible data structure for host compatibility and system performance
Supports 25 to 33 Mhz PCI clock speed
Supports full MII management function
Provides EEPROM and flash memory on-board programming function
Supports both big and little endian byte ordering for descriptor and buffer
Flexible address filtering modes
-- 64-bit hash-table and one perfect address
-- All multicast and promiscuous
A boot ROM interface, capable of supporting up to 256KB
Supports programmable sub-vendor ID with automatic loading into configuration register
Internal and external loopback mode for diagnostic
Single 5 volt power supply
100 pins PQFP package
Supports PCI bus master mode for DMA operation, fully complying with PCI 2.1 standard
Early interrupt function available for both transmit and receive
Both half duplex and full duplex available
Independent deep receive and transmit FIFO and no onboard memory required
Flexible data structure for host compatibility and system performance
Supports 25 to 33 Mhz PCI clock speed
Supports full MII management function
Provides EEPROM and flash memory on-board programming function
Supports both big and little endian byte ordering for descriptor and buffer
Flexible address filtering modes
-- 64-bit hash-table and one perfect address
-- All multicast and promiscuous
A boot ROM interface, capable of supporting up to 256KB
Supports programmable sub-vendor ID with automatic loading into configuration register
Internal and external loopback mode for diagnostic
Single 5 volt power supply
100 pins PQFP package
W89C840F Connection Diagram
W89C841F General Description
W89C841F is a highly integrated PCI Fast Ethernet MAC controller with embedded Ethernet transceiver for 100BaseTX, 100BaseFX and 10BaseT. It is compliant with IEEE 802.3, 802.3u specification. Auto cross-over function is supported on TP terminal and the network status of W89C841F is indicated by 3 LED pins. W89C841F supports full/half duplex, asymmetrical flow control operation compliant with IEEE 802.3x and VLAN tagged frame compliant with IEEE 802.1p.
According to different applications, W89C841F can be configured into one of 3 modes to operate by setting the pins CONFIG[1:0] and ModeSel[2:0] after power-on reset. The 3 operational modes of W89C841F are listed as below.
1. PCI Ethernet MAC controller with internal Ethernet PHYceiver.
2. Pure PCI Ethernet MAC Controller
3. Pure 10/100M PHYceiver
W89C841F provides a host bus interface complying with the PCI local bus specification R2.2, Mini PCI Specification R1.0 and CardBus. W89C841F plays as a bus master role to improve network performance and reduce the bus utilization. There are built-in 2K bytes TX FIFO and 2K bytes RX FIFO to store data. The DMA controller handles the data transfer between the host memory and the FIFOs. The data received from network are queued into the RX FIFO then directly moved into the host memory through the PCI bus. On the other hand, the transmitted data are fetched from the host memory and directly queued into the transmit FIFO. No extra on-board memory is needed for data buffering during operation.
For PC99/2001, W89C841F implements power management function that are compliant with Advanced Configuration and Power Interface (ACPI) specification R1.0, PCI Power Management Interface specification R1.1 and Network Device Class Power Management Reference specification V1.0a. W89C841F supports D3cold power management state if auxiliary power is detected. 3 types of wakeup events are acceptable like link status change, Magic Packet and 5 sets of wake-up frames.
EEPROM (93C46) is supported by W89C841F to store configuration and Vital Product Data (VPD) information. The length of VPD information is up to 64 bytes. W89C841F can access the CardBus information Structure (CIS) information that is stored at EEPROM (93C56) or BootROM. W89C841F also supports BootROM/Flash interface to read/write BootROM or Flash memory.
W89C841F Maximum Ratings
| PARAMETER |
SYMBOL |
MIN. |
MAX. |
UNIT |
| Operating Temperature |
TA |
0 |
70 |
°C |
| Storage Temperature |
TS |
-55 |
125 |
°C |
| Supply Voltage |
VCC_core VCC_IO |
2.25 3.0 |
2.75 3.6 |
V |
| Input Voltage |
VIN |
VSS |
5 + 0.5 |
V |
| Output Voltage |
VOUT |
VSS |
3.6 |
V |
W89C841F Features
· Integrated Fast Ethernet MAC controller with10/100M Ethernet transceiver in one chip
· Supports MII interface for programmable single PHYceiver or single MAC controller
· Complies with IEEE 802.3, 802.3u specification
· Supports 10BAST-T, 100BASE-TX and 100BASE-FX
· Supports auto cross-over operation
· Supports half duplex and full duplex for 10/100M operation
· Supports flow control for full duplex mode compliant with IEEE 802.3x
· Complies with IEEE802.3ac, 802.1Q for VLAN-tagged frame
· Supports LED pins for network activity indication
· Configurable to PCI, MiniPCI or CardBus bus interface
· Supports PCI/MiniPCI bus master mode for DMA operation, fully compliant with PCI Local Bus
Specification R2.2 and Mini PCI Specification R1.0
· Supports CardBus Information Structure (CIS)
· Supports 25 to 33 MHz PCI clock speed
· Compliant with APCI R1.0, PCI power management R1.1 and Network device Class Power
management Reference specification V1.0a
· Supports power management event asserted from D3(cold) device state with auxiliary power existing
· Supports wakeup function for Link status change, Magic Packet and 5 sets of wakeup frames
· Supports Vital Product Data (VPD) data structure up to 64 Bytes
· Supports 2 sets of independent embedded 2K bytes FIFO for transmit and receive
· Flexible multicast address filtering modes
- 64-bit hash-table
- All multicast and promiscuous
· Supports 25 MHz crystal or oscillator as internal clock source
· Provides EEPROM (93C46 or 93C56) to store configuration parameters, VPD, and CIS information
· Supports 8KB to 256 KB BootROM interface for both PROM and Flash memory
· 3.3V powered I/Os with 5V tolerant inputs
· Packaged in 128-pin PQFP for W89C841F/ LQFP for W89C841D
· Supports MII interface for programmable single PHYceiver or single MAC controller
· Complies with IEEE 802.3, 802.3u specification
· Supports 10BAST-T, 100BASE-TX and 100BASE-FX
· Supports auto cross-over operation
· Supports half duplex and full duplex for 10/100M operation
· Supports flow control for full duplex mode compliant with IEEE 802.3x
· Complies with IEEE802.3ac, 802.1Q for VLAN-tagged frame
· Supports LED pins for network activity indication
· Configurable to PCI, MiniPCI or CardBus bus interface
· Supports PCI/MiniPCI bus master mode for DMA operation, fully compliant with PCI Local Bus
Specification R2.2 and Mini PCI Specification R1.0
· Supports CardBus Information Structure (CIS)
· Supports 25 to 33 MHz PCI clock speed
· Compliant with APCI R1.0, PCI power management R1.1 and Network device Class Power
management Reference specification V1.0a
· Supports power management event asserted from D3(cold) device state with auxiliary power existing
· Supports wakeup function for Link status change, Magic Packet and 5 sets of wakeup frames
· Supports Vital Product Data (VPD) data structure up to 64 Bytes
· Supports 2 sets of independent embedded 2K bytes FIFO for transmit and receive
· Flexible multicast address filtering modes
- 64-bit hash-table
- All multicast and promiscuous
· Supports 25 MHz crystal or oscillator as internal clock source
· Provides EEPROM (93C46 or 93C56) to store configuration parameters, VPD, and CIS information
· Supports 8KB to 256 KB BootROM interface for both PROM and Flash memory
· 3.3V powered I/Os with 5V tolerant inputs
· Packaged in 128-pin PQFP for W89C841F/ LQFP for W89C841D
W89C841F Connection Diagram
MT58L64L18CT-10
Price: 4-6 USD
MT58L64L18CT-10 TQFP100
DL-7140-211M
Price: 5-6.5 USD
DL-7140-211M laser tube
74LVC74APG
Price: 4-5 USD
74LVC74APG - IC FLIP FLOP D-Type POS-EDG DUAL 14TSSOP
CY28346ZI-2
Price: 6.5-8 USD
CYPRESS - Clock Synthesizer with Differential CPU Outputs
PI5V330QEX
Price: 0.284-0.286 USD
PI5V330QEX Pericom Multiplexer Switch ICs
BSM300GA120DN2
Price: 1-2 USD
IGBT power module, Single switch, 1200 V, Collector-emitter voltage, 430A
SVA150XG04TB
Price: 1-2 USD
a-Si TFT-LCD, NEC, 228.096Hmm, 560V
PC354N1
Price: 0.124-0.2 USD
PC354N1T - Mini-flat Package, AC Input Type Photocoupler - Sharp Electrionic Components
RL1210JR-070R22L
Price: 0.177-0.178 USD
RL1210JR51-XX-BL - Thick Film Chip Resistor Low Ohmic - TAITRON Components Incorporated
STPS140A
Price: 0.053-0.055 USD
STPS140A - POWER SCHOTTKY RECTIFIER - STMicroelectronics
STA013
Price: 1.45-1.5 USD
STA013 - MPEG 2.5 LAYER III AUDIO DECODER - STMicroelectronics
SMBJ5347B
Price: 0.073-0.075 USD
SMBJ5347B - 5 Watt Surface Mount Silicon Zener Diodes - Micro Commercial Components
