VT8633, VT86C100A, VT86C916 Selling Leads, Datasheet
MFG:VIA Package Cooled:0108+ D/C:BGA
VT8633, VT86C100A, VT86C916 Datasheet download
Part Number: VT8633
MFG: VIA
Package Cooled: 0108+
D/C: BGA
VT8633, VT86C100A, VT86C916
- Table of contents:
Info of VT8633
Info of VT86C100A
Info of VT86C916
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About VT800
PDF/DataSheet Download
Datasheet: VT800
File Size: 1270598 KB
Manufacturer: PERKINELMER [PerkinElmer Optoelectronics]
Download : Click here to Download
About VT86C100A
PDF/DataSheet Download
Datasheet: VT86C100A
File Size: 357563 KB
Manufacturer: ETC [ETC]
Download : Click here to Download
About VT800
PDF/DataSheet Download
Datasheet: VT800
File Size: 1270598 KB
Manufacturer: PERKINELMER [PerkinElmer Optoelectronics]
Download : Click here to Download
VT86C100A General Description
The VT86C100A Rhine ACPI PCI bus master 100 M FAST Ethernet controller is CMOS VLSI designed for easy implementation of CSMA/CD IEEE 802.3u 100M local area networks. Significant features include: twisted-pair interface, PCI Plug&Play compatibility, 32 bit bus mastering, powerful buffer management and Early Interrupt Receive/Transmit.
The VT86C100A integrates the entire bus interface of PCI systems. Setting hardware jumpers or software configures the VT86C100A bus interface. The VT86C100A also complies with PCI specification v2.1.. The VT86C100A supports the Media Independent Interface (MII) network interface.
VT86C100A Features
* Single chip Fast Ethernet controller for PCI bus interface
-- compliant to PCI v2.1 with optional delay transaction and sub-vendor, sub-system- ID
-- Provides a direct connection to PCI bus
-- Supports two network ports : 10/100 M MII interface
* High performance PCI mastering structure
-- VIA self-define 128 bytes memory I/O or register I/O based command and status register
-- Software oriented chain structure description to minimize hardware complexity
-- Include on chip bus master DMA with programmable burst length for low CPU utilization
-- Dynamic transmit packet auto queuing for back auto queuing for bac for back to back transmissin
-- Programmable activity polling intervals for description DMA
-- Programmable DMA arbitration priority to minimize overflow under flow condition
-- Support early receive and early transmit interrupt for software parallel processing
-- Interrupt controllable by receive/transmit descriptor list for saving interrupt service time
* Provides standard 100-M bits MII interface
-- Support 100Base-TX with CAT5 UTP, STP and fiber cables
-- Support 100Base-T4 with CAT3, CAT4, CAT 5 UTP, STP
* 10/100Mhz full duplex, half duplex operation
* Contains two deeper 2K bytes FIFO for receive and transmit controller both supports bursts of up to full Ethernet length
-- Programmable receive and transmit FIFO threshold control for optimize PCI throughput
* Flexible dynamically load EEPROM algorithm.
-- Load after power-up
-- Dynamic auto reload
-- Embedded programming for configure modification
-- Dynamic direct programming for manufacturing
* Support physical, Broadcast, Multicast address filtering using hashing function
* Support Magic packet and wake on address filtering
* Support external Bootrom up to 64K bytes no external address latch
* Software controllable power down feature
* Single +5V supply, 0.5um standard CMOS technology
* 128 pin PQFP package
-- compliant to PCI v2.1 with optional delay transaction and sub-vendor, sub-system- ID
-- Provides a direct connection to PCI bus
-- Supports two network ports : 10/100 M MII interface
* High performance PCI mastering structure
-- VIA self-define 128 bytes memory I/O or register I/O based command and status register
-- Software oriented chain structure description to minimize hardware complexity
-- Include on chip bus master DMA with programmable burst length for low CPU utilization
-- Dynamic transmit packet auto queuing for back auto queuing for bac for back to back transmissin
-- Programmable activity polling intervals for description DMA
-- Programmable DMA arbitration priority to minimize overflow under flow condition
-- Support early receive and early transmit interrupt for software parallel processing
-- Interrupt controllable by receive/transmit descriptor list for saving interrupt service time
* Provides standard 100-M bits MII interface
-- Support 100Base-TX with CAT5 UTP, STP and fiber cables
-- Support 100Base-T4 with CAT3, CAT4, CAT 5 UTP, STP
* 10/100Mhz full duplex, half duplex operation
* Contains two deeper 2K bytes FIFO for receive and transmit controller both supports bursts of up to full Ethernet length
-- Programmable receive and transmit FIFO threshold control for optimize PCI throughput
* Flexible dynamically load EEPROM algorithm.
-- Load after power-up
-- Dynamic auto reload
-- Embedded programming for configure modification
-- Dynamic direct programming for manufacturing
* Support physical, Broadcast, Multicast address filtering using hashing function
* Support Magic packet and wake on address filtering
* Support external Bootrom up to 64K bytes no external address latch
* Software controllable power down feature
* Single +5V supply, 0.5um standard CMOS technology
* 128 pin PQFP package
VT86C100A Connection Diagram
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