MFG:Texas Instruments Category:Integrated Circuits (ICs) Package Cooled:N/S D/C:08.09+
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TVP7001PZP, TVP7001PZPG4, TVP7002 Datasheet download
Category: Integrated Circuits (ICs)
MFG: Texas Instruments
Package Cooled: N/S
D/C: 08.09+
Description: IC VIDEO DIGITIZER 100-HTQFP
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PDF/DataSheet Download
Datasheet: TVP2002FN
File Size: 402417 KB
Manufacturer:
Download : Click here to Download
PDF/DataSheet Download
Datasheet: TVP2002FN
File Size: 402417 KB
Manufacturer:
Download : Click here to Download
PDF/DataSheet Download
Datasheet: TVP2002FN
File Size: 402417 KB
Manufacturer:
Download : Click here to Download
| Technical/Catalog Information | TVP7001PZP |
| Vendor | Texas Instruments |
| Category | Integrated Circuits (ICs) |
| Mounting Type | Surface Mount |
| Package / Case | 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP |
| Type | Video Digitizer |
| Packaging | Tray |
| Applications | Monitors, Projectors, Set-Top Boxes |
| Drawing Number | 296; 4146929; PZP; 100 |
| Lead Free Status | Lead Free |
| RoHS Status | RoHS Compliant |
| Other Names | TVP7001PZP TVP7001PZP 296 19616 ND 29619616ND 296-19616 |
TVP7002 is a complete solution for digitizing video and graphic signals in RGB or YPbPr color spaces. The device supports pixel rates up to 165 MHz. Therefore, it can be used for PC graphics digitizing up to the VESA standard of UXGA (1600 ×1200) resolution at 60-Hz screen refresh rate, and in video environments for the digitizing of digital TV formats, including HDTV up to 1080p.
The TVP7002 is powered from 3.3-V and 1.9-V supply and integrates a triple high-performance analog-to-digital (A/D) converter with clamping functions and variable gain, independently programmable for each channel. The clamp timing window is provided by an external pulse or can be generated internally. TheTVP7002 includes analog slicing circuitry on the SOG inputs to support sync-on-luminance or sync-on-green extraction. In addition, TVP7002 can extract discrete HSYNC and VSYNC from composite sync using a sync slicer.
TVP7002 also contains a complete horizontal PLL block to generate a pixel clock from the HSYNC input. Pixel clock output frequencies range from 12 MHz to 165 MHz.
All programming of the part is done via an industry-standard I2C interface, which supports both reading and writing of register settings. The TVP7002 is available in a space-saving 100-pin TQFP PowerPAD package.
| Supply voltage range | IOVDD to IOGND | 0.5 V to 4.5 V | |
| DVDD to DGND | 0.5 V to 2.3 V | ||
| PLL_AVDD to PLL_AGND and AVDD to AGND | 0.5 V to 2.3 V | ||
| A33VDD to A33GND | 0.5 V to 4.5 V | ||
| Digital input voltage range | VI to DGND | 0.5 V to 4.5 V | |
| Analog input voltage range | AI to A33GND | 0.2 V to 2.3 V | |
| Digital output voltage range | AI to A33GND | 0.5 V to 4.5 V | |
| TA | AI to A33GND | 0 to 70 | |
| Tstg | Storage temperature range | 0 to 70 | |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
` Analog Channels
- -6-dB to 6-dB Analog Gain
Analog Input Multiplexers (MUXs)
Automatic Video Clamp
Three Digitizing Channels, Each With Independently Controllable Clamp, Gain,
Offset, and Analog-to-Digital Converter (ADC)
Clamping: Selectable Clamping Between Bottom Level and Mid-Level
Offset: 1024-Step Programmable RGB or YPbPr Offset Control
Gain: 8-Bit Programmable Gain Control
ADC: 8-/10-Bit 165-/110-MSPS ADC
Automatic Level Control (ALC) Circuit
Composite Sync: Integrated Sync-on-Green Extraction From Green/Luminance Channel
Support for DC- and AC-Coupled Input Signals
Supports Component Video Standards 480i, 576i, 480p, 576p, 720p, 1080i, and 1080p
Supports PC Graphics Inputs up to UXGA
Programmable RGB-to-YCbCr Color Space Conversion
` Horizontal PLL
Fully Integrated Horizontal PLL for Pixel Clock Generation
12-MHz to 165-MHz Pixel Clock Generation From HSYNC Input
Adjustable Horizontal PLL Loop Bandwidth for Minimum Jitter
5-Bit Programmable Subpixel Accurate Positioning of Sampling Phase
` Output Formatter
Supports 20-bit 4:2:2 Outputs With Embedded Syncs
Support for RGB/YCbCr 4:4:4 and YCbCr 4:2:2 Output Modes to Reduce Board Traces
Dedicated DATACLK Output With Programmable Output Polarity for Easy Latching of
Output Data
` System
Industry-Standard Normal/Fast I2C Interface With Register Readback Capability
Space-Saving 100-Pin TQFP Package
Thermally-Enhanced PowerPAD™ Package for Better Heat Dissipation
Glueless Interface to TVP9000/9001 Video Processor Back-End Devices
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