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TC59LM818DMG-33, TC59LM836DKB-30B, TC59PM716GM-8

Table of contents:
Info of TC59LM818DMG-33
Info of TC59LM836DKB-30B
Info of TC59PM716GM-8

TC59LM818DMG-33, TC59LM836DKB-30B, TC59PM716GM-8 Selling Leads, Datasheet

MFG:TOSHIBA Package Cooled:CBGA D/C:09+

TC59LM818DMG-33, TC59LM836DKB-30B, TC59PM716GM-8 Picture

TC59LM818DMG-33, TC59LM836DKB-30B, TC59PM716GM-8 Datasheet download

Five Points

Part Number: TC59LM818DMG-33

MFG: TOSHIBA

Package Cooled: CBGA

D/C: 09+

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TC59LM818DMG-33 General Description

Network FCRAM^TM is Double Data Rate Fast Cycle Random Access Memory. TC59LM818DMG is Network FCRAM^TM containing 301,989,888 memory cells. TC59LM818DMG is organized as 4,194,304-words × 4 banks × 18 bits. TC59LM818DMG feature a fully synchronous operation referenced to clock edge whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. TC59LM818DMG can operate fast core cycle compared with regular DDR SDRAM.

TC59LM818DMG is suitable for Network, Server and other applications where large memory density and low power consumption are required. The Output Driver for Network FCRAMTM is capable of high quality fast data transfer under light loading condition.

TC59LM818DMG-33 Maximum Ratings

SYMBOL	PARAMETER	RATING	UNIT	NOTES
V_DD V_DDQ V_IN V_OUT V_REF T_opr T_stg T_solder P_DI_OUT	Power Supply Voltage Power Supply Voltage (for DQ buffer)Input Voltage Output and DQ pin Voltage Input Reference Voltage Operating Temperature (case)Storage Temperature Soldering Temperature (10 s) Power Dissipation Short Circuit Output Current	−0.3~ 3.3 −0.3~V_DD+ 0.3 −0.3~V_DD+ 0.3 0.3~V_DDQ + 0.3 −0.3~V_DD+ 0.3 0~85 −55~150 260 2 ±50	V V V V V °C °C °C W mA

Caution: Conditions outside the limits listed under "ABSOLUTE MAXIMUM RATINGS" may cause permanent damage to the device. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to "ABSOLUTE MAXIMUM RATINGS" conditions for extended periods may affect device reliability.

TC59LM818DMG-33 Features

• Fully Synchronous Operation
• Double Data Rate (DDR) Data input/output are synchronized with both edges of DS / QS.
• Differential Clock (CLK and CLK ) inputs CS , FN and all address input signals are sampled on the positive edge of CLK. Output data (DQs and QS) is aligned to the crossings of CLK and CLK .
• Fast clock cycle time of 3.0 ns minimum Clock: 333 MHz maximum Data: 666 Mbps/pin maximum
• Quad Independent Banks operation
• Fast cycle and Short Latency
• Selectable Data Strobe
• Distributed Auto-Refresh cycle in 3.9 s
• Self-Refresh
• Power Down Mode
• Variable Write Length Control
• Write Latency = CAS Latency-1
• Programable CAS Latency and Burst Length CAS Latency = 4, 5, 6 Burst Length = 2, 4
• Organization: 2,097,152 words * 4 banks * 36 bits
• Power Supply Voltage V_DD: 2.5 V ± 0.125V V_DDQ: 1.4 V ~ 1.9 V
• Low voltage CMOS I/O covered with SSTL_18 (Half strength driver) and HSTL.
• JTAG boundary scan
• Package: 144Ball BGA, 1mm * 0.8mm Ball pitch (P-TFBGA144-1119-0.80BZ)
Notice: FCRAM is trademark of Fujitsu limited, Japan.

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