T8521AM, T8533, T8533ML Selling Leads, Datasheet
MFG:TOS Package Cooled:SMD D/C:09+
T8521AM, T8533, T8533ML Datasheet download
Part Number: T8521AM
MFG: TOS
Package Cooled: SMD
D/C: 09+
T8521AM, T8533, T8533ML
- Table of contents:
Info of T8521AM
Info of T8533
Info of T8533ML
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About T8502
PDF/DataSheet Download
Datasheet: T8502
File Size: 451352 KB
Manufacturer: AGERE [Agere Systems]
Download : Click here to Download
About T8533
PDF/DataSheet Download
Datasheet: T8533
File Size: 912312 KB
Manufacturer: AGERE [Agere Systems]
Download : Click here to Download
About T8502
PDF/DataSheet Download
Datasheet: T8502
File Size: 451352 KB
Manufacturer: AGERE [Agere Systems]
Download : Click here to Download
T8533 General Description
The quad programmable line card signal processor consists of four independent channels of codec and digital signal processing functions on one chip. In addition to the classic A-to-D and D-to-A conversion, the device includes termination impedance synthesis and a 64-tap echo canceller, functionally, on a perchannel basis. The device is capable of meeting all international standards for terminating impedance and digital encoding format. The processing circuitry for the adjustment of the transmit level (equalization) to accommodate current-sensing SLICs is also included.
The device is controlled by a serial microprocessor interface, and a set of bidirectional I/O pins are provided, on a per-channel basis, so that this control mechanism can be utilized to operate the battery feed device, ringing voltage switches, etc. Common data and clock paths can be shared over any number of devices. All the filter coefficients, signal processing, SLIC, and test features are accessible through this interface. This serial interface can be operated at speeds up to 4.096 Mbits/s.
The PCM bus is also programmable, with any channel capable of being assigned to any time slot. The PCM bus can be operated at speeds up to 16.384 Mbits/s, allowing for a maximum of 256 time slots. Separate transmit and receive interfaces are available for 4-wire bus designs, or they can be strapped together for a 2-wire PCM bus.
The device is available in 68-pin, 64-pin, and 44-pin surface-mount packages for economic use of board space.
The device is controlled by a serial microprocessor interface, and a set of bidirectional I/O pins are provided, on a per-channel basis, so that this control mechanism can be utilized to operate the battery feed device, ringing voltage switches, etc. Common data and clock paths can be shared over any number of devices. All the filter coefficients, signal processing, SLIC, and test features are accessible through this interface. This serial interface can be operated at speeds up to 4.096 Mbits/s.
The PCM bus is also programmable, with any channel capable of being assigned to any time slot. The PCM bus can be operated at speeds up to 16.384 Mbits/s, allowing for a maximum of 256 time slots. Separate transmit and receive interfaces are available for 4-wire bus designs, or they can be strapped together for a 2-wire PCM bus.
The device is available in 68-pin, 64-pin, and 44-pin surface-mount packages for economic use of board space.
T8533 Features
· Includes codec, termination impedance, and echo canceller in one device for line card applications
· Programmable m-law, linear, or A-law PCM inputand output (ITU-T G.712 compliant)
· Per-channel programmable gains
· Per-channel programmable internal terminationimpedance
· Per-channel 64-tap echo canceller (ITU-T G.168compliant)
· Fully programmable time-slot assignment
· Analog and digital loopback test modes
· Serial microprocessor interface
· Sigma-delta converters with dither to reduce noise
· Six per-channel, bidirectional control pins for SLICand line card function control (68-pin package)
· Quad design to minimize package count on denseline card applications
· Built-in level correction (transmit equalization) toaccommodate current-sensing SLICs
· Single 5 V operation
· Available in 68-pin, 64-pin, and 44-pin packages
· Programmable m-law, linear, or A-law PCM inputand output (ITU-T G.712 compliant)
· Per-channel programmable gains
· Per-channel programmable internal terminationimpedance
· Per-channel 64-tap echo canceller (ITU-T G.168compliant)
· Fully programmable time-slot assignment
· Analog and digital loopback test modes
· Serial microprocessor interface
· Sigma-delta converters with dither to reduce noise
· Six per-channel, bidirectional control pins for SLICand line card function control (68-pin package)
· Quad design to minimize package count on denseline card applications
· Built-in level correction (transmit equalization) toaccommodate current-sensing SLICs
· Single 5 V operation
· Available in 68-pin, 64-pin, and 44-pin packages
T8533 Typical Application
The following reference circuit shows a complete schematic for interfacing to the Agere L9215G SLIC. All ac
parameters are programmed by the T8534. Note that this implementation differentiates itself in that no external
components are required in the ac interface to provide a dc termination impedance or for stability. For illustration
purposes, 0.5 Vrms PPM injection was assumed in this example and no meter pulse rejection is used. Also, this
example illustrates the device using programmable overhead and current limit.
parameters are programmed by the T8534. Note that this implementation differentiates itself in that no external
components are required in the ac interface to provide a dc termination impedance or for stability. For illustration
purposes, 0.5 Vrms PPM injection was assumed in this example and no meter pulse rejection is used. Also, this
example illustrates the device using programmable overhead and current limit.
T8533 Connection Diagram
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