T8302, T8302 BAL, T83027-S08 Selling Leads, Datasheet
MFG:ST Package Cooled:TO D/C:09+
T8302, T8302 BAL, T83027-S08 Datasheet download
Part Number: T8302
MFG: ST
Package Cooled: TO
D/C: 09+
T8302, T8302 BAL, T83027-S08
- Table of contents:
Info of T8302
Info of T8302 BAL
Info of T83027-S08
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About T8302
PDF/DataSheet Download
Datasheet: T8302
File Size: 7496734 KB
Manufacturer: AGERE [Agere Systems]
Download : Click here to Download
About T8301
PDF/DataSheet Download
Datasheet: T8301
File Size: 1572824 KB
Manufacturer: AGERE [Agere Systems]
Download : Click here to Download
About T8301
PDF/DataSheet Download
Datasheet: T8301
File Size: 1572824 KB
Manufacturer: AGERE [Agere Systems]
Download : Click here to Download
T8302 Maximum Ratings
|
Parameter |
Symbol |
Min |
Max |
Unit |
| Supply Voltage |
- |
- |
3.5 |
V |
| XRTC0, XRTC1, XTAL0, XTAL1, XLO, XHI |
- |
VSS |
VDD |
V |
| Voltage Applied to I/O Pins |
- |
VDD0.3 |
5.5 |
V |
| Operating Temperature |
- |
0 |
70 |
°C |
| Storage Temperature |
- |
-40 |
125 |
°C |
T8302 Features
· Compliant with ISO* 8802.3 1993, IEEE† 802.3u 1995, and IEEE 802.3x 1995 standards for media access control.
· Data transmission and reception rates of 10 Mbits/s at a clock speed of 2.5 MHz or 100 Mbits/s at a clock speed
of 25 MHz.
· Transmits or receives at full- or half-duplex.
· Supports flow control.
· Supports both VLAN type1 and VLAN type2 frame recognition.
· Extensive network management signals are provided.
· Transmit and receive functions can be asynchronously reset with no clocks present.
· Supports full internal scan test methodology.
· Retransmit capability on early collision detection.
· Flexible arithmetic or logical physical address matching.
· Queued storage of packet reception status and byte counts for relaxed real-time interrupt latency requirements.
· 128 bytes of FIFO buffering in both the transmit and receive directions.
· Easy setup of control or pause frame transmission for network control.
· Data transmission and reception rates of 10 Mbits/s at a clock speed of 2.5 MHz or 100 Mbits/s at a clock speed
of 25 MHz.
· Transmits or receives at full- or half-duplex.
· Supports flow control.
· Supports both VLAN type1 and VLAN type2 frame recognition.
· Extensive network management signals are provided.
· Transmit and receive functions can be asynchronously reset with no clocks present.
· Supports full internal scan test methodology.
· Retransmit capability on early collision detection.
· Flexible arithmetic or logical physical address matching.
· Queued storage of packet reception status and byte counts for relaxed real-time interrupt latency requirements.
· 128 bytes of FIFO buffering in both the transmit and receive directions.
· Easy setup of control or pause frame transmission for network control.
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