Want to post a buying lead? If you are not a member yet, please select the specific/related part number first and then fill the quantity and your contact details in the "Request for Quotation Form" on the left, and then click "Send RFQ".Your buying lead can then be posted, and the reliable suppliers will quote via our online message system or other channels soon.
The SY89809L is a High-Performance Bus Clock Driver with 9 differential HSTL (High-Speed Transceiver Logic) output pairs. The part is designed for use in low-voltage (3.3V/1.8V) applications which require a large number of outputs to drive precisely aligned, ultralow skew signals to their destination. The input is multiplexed from either HSTL or LVPECL (Low-Voltage Positive-Emitter-Coupled Logic) by the CLK_SEL pin. The Output Enable (OE) is synchronous so that the outputs will only be enabled/ disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control.
The SY89809L features low pin-to-pin skew (50ps max.) and low part-to-part skew (200ps max.)-performance previously unachievable in a standard product having such a high number of outputs. The SY89809L is available in a single space saving package, enabling a lower overall cost solution.
SY89809L Maximum Ratings
Symbol
Rating
Value
Unit
VCCI/VCCO
VCC Pin Potential to Ground Pin
0.5 to +6.0
V
VIN
Input Voltage
-0.5 to VCC+0.5
V
IOUT
DC Output Current (Output HIGH)
-50
mA
Tstore
Storage Temperature Range
65 to +150
°C
SY89809L Features
3.3V core supply, 1.8V output supply for reduced power LVPECL and HSTL inputs 9 differential HSTL (low-voltage swing) output pairs HSTL outputs drive 50 to ground with no offset voltage Low part-to-part skew (200ps max.) Low pin-to-pin skew (50ps max.) Available in 32-pin TQFP package
SY89809L Typical Application
High-performance PCs Workstations Parallel processor-based systems Other high-performance computing Communication