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SY87701V

Features: 3.3V and 5V power supply options Clock and data recovery from 32Mbps up to 1.25Gbps NRZ data stream Complies with Bellcore, ITU/CCITT and ANSI specifications for applications such as OC-1, OC-3, OC-12, ATM, FDDI, etc. Two on-chip PLLs: one for clock generation and another for clock recov...

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SeekIC No. : 004510235 Detail

SY87701V: Features: 3.3V and 5V power supply options Clock and data recovery from 32Mbps up to 1.25Gbps NRZ data stream Complies with Bellcore, ITU/CCITT and ANSI specifications for applications such as OC-1,...

SY87701V Data Sheet

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Part Number:
SY87701V
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/30

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Product Details

Description



Features:

 3.3V and 5V power supply options
Clock and data recovery from 32Mbps up to 1.25Gbps NRZ data stream
Complies with Bellcore, ITU/CCITT and ANSI specifications for applications such as OC-1, OC-3,
       OC-12, ATM, FDDI, etc.
Two on-chip PLLs: one for clock generation and another for clock recovery
Selectable reference frequencies
Differential PECL high-speed serial I/O
Line receiver input: no external buffering needed
Link fault indication
100K ECL compatible I/O
Available in 28-pin SOIC and 32-pin EP-TQFP packages


Application

SONET/SDH/ATM OC-1, OC-3, OC-12, OC-24
Fibre Channel, Escon
Gigabit Ethernet/Fast Ethernet
Proprietary architecture up to 1.25Gbps


Pinout

Connection Diagram


Specifications

Symbol Parameter Value Unit
VCC Power Supply 0.5 to +7.0 V
VI Input Voltage 0.5 to VCC V
IOUT ECL Output Current
          - Continuous
          - Surge		 50
100		 mA
Tstore Storage Temperature 65 to +150 °C
TA Operating Temperature 0 to +85 °C
JA Thermal Resistance
@still air		 80 single
air layer board,
46 multi-layer		 °C/W



Description

The SY87701V is a complete Clock Recovery and Data Retiming integrated circuit for data rates from 32Mbps up to 1.25Gbps NRZ. The device is ideally suited for SONET/SDH/ATM and Fibre Channel applications and other high-speed data transmission systems.

Clock recovery and data retiming is performed by synchronizing the on-chip VCO directly to the incoming data stream. The VCO center frequency is controlled by the reference clock frequency and the selected divide ratio. On-chip clock generation is performed through the use of a frequency multiplier PLL with a byte rate source as reference.The SY87701V also includes a link fault detection circuit.




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