SDA5522-PO-A003, SDA5523, SDA5523A002 Selling Leads, Datasheet
MFG:MICRONAS Package Cooled:DIP D/C:02+
SDA5522-PO-A003, SDA5523, SDA5523A002 Datasheet download
Part Number: SDA5522-PO-A003
MFG: MICRONAS
Package Cooled: DIP
D/C: 02+
MFG:MICRONAS Package Cooled:DIP D/C:02+
SDA5522-PO-A003, SDA5523, SDA5523A002 Datasheet download
MFG: MICRONAS
Package Cooled: DIP
D/C: 02+
Want to post a buying lead? If you are not a member yet, please select the specific/related part number first and then fill the quantity and your contact details in the "Request for Quotation Form" on the left, and then click "Send RFQ".Your buying lead can then be posted, and the reliable suppliers will quote via our online message system or other channels soon.
TOP
PDF/DataSheet Download
Datasheet: SDA01
File Size: 21011 KB
Manufacturer: SANKEN [Sanken electric]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: SDA01
File Size: 21011 KB
Manufacturer: SANKEN [Sanken electric]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: SDA01
File Size: 21011 KB
Manufacturer: SANKEN [Sanken electric]
Download : Click here to Download
The on-chip clock generator provides the TVTpro with its basic clock signal. The oscillator runs with an external crystal and the appropriate internal oscillator circuitry (see Fig. on page 174).
For applications with lower timing accuracy requirements (and if the RTC is not used) an external ceramic resonator can be used. The usage of a ceramic resonator is not recommended for Teletext applications as depending on the absolute tolerance of the ceramic resonator the data slicer may not work correctly. Additional this might also require that display timing parameters and the baud rate prescaler have to be adapted.
In timing critical applications the horizontal frequency of the incoming CVBS signal can be used to measure the actual timing deviation and to re-program the clock PLL.
The 6 MHz clock signal is used to generate the internal 300 MHz display reference clock by means of an onchip phase locked loop (PLL). The PLL can be bypassed to reduce the power consumption. If an immediate wake up from power down is not required the PLL can also be switched off in this mode. From the output frequency of the main clock PLL two clock systems are derived.
Symbol |
Parameter | Pin Name | Pin Name | Unit | |
Min | Max | ||||
TA |
Ambient Temperature PSDIP52-1, PSDIP52-2 1) PMQFP64-1 PLCC84-1 PMQFP100-1 |
−10 −10 −10 −10 |
70 70 70 70 |
°C °C °C °C | |
TC |
Case Temperature PSDIP52-1, PSDIP52-2 1 PMQFP64-1 PLCC84-1 PMQFP100-1 |
15 15 15 15 |
85 85 85 85 |
°C °C °C °C | |
TS |
Storage Temperature | -20 | 125 | °C | |
Pmax |
Maximum Power Dissipation PSDIP52-1, PSDIP52-2 1) PMQFP64-1 PLCC84-1 PMQFP100-1 |
0.6 0.6 0.6 0.6 |
W | ||
VDD331..7 | Supply Voltage 3.3 V | 3 | 3.6 | V | |
VDD251..2 | Supply Voltage 2.5 V | 2.25 | 2.75 | - | |
VDDA1..4 | Analog Supply Voltage | 2.25 | 2.75 | - | |
1) Single chip. Not applicable for Flash version (SDA 555xFL) |