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SAA6578T, SAA6579, SAA6579(DIP)

Table of contents:
Info of SAA6578T
Info of SAA6579
Info of SAA6579(DIP)

SAA6578T, SAA6579, SAA6579(DIP) Selling Leads, Datasheet

MFG:PHI Package Cooled:SOP D/C:05/06+

SAA6578T, SAA6579, SAA6579(DIP) Datasheet download

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Part Number: SAA6578T

MFG: PHI

Package Cooled: SOP

D/C: 05/06+

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SAA6579 General Description

The integrated CMOS circuit SAA6579 is an RDS demodulator. It recovers the additional inaudible RDS information which is transmitted by FM radio broadcasting. The data signal RDDA and the clock signal RDCL are provided as outputs for further processing by a suitable decoder (microcomputer).

The operational functions of the device are in accordance with the "CENELEC EN 50067".

SAA6579 Maximum Ratings

SYMBOL	PARAMETER	CONDITIONS	MIN.	MAX.	UNIT
V_DDA	analog supply voltage (pin 5)		0	6	V
V_DDD	digital supply voltage (pin 12)		0	6	V
V_n	voltage on all pins; grounds excluded		-0.5	V_DDX + 0.5	V
T_stg	storage temperature		-40	+150	°C
T_amb	operating ambient temperature		-40	+85	°C
V_es	electrostatic handling for all pins except pins 9 and 10	note 1	±300	-	V
V_es	electrostatic handling for all pins except pins 9 and 10	note 2	+1500	-3000	V

Notes
1. Equivalent to discharging a 200 pF capacitor via a 0 series resistor.
2. Equivalent to discharging a 100 pF capacitor via a 1.5 k series resistor.

SAA6579 Features

· Anti-aliasing filter (2nd order)
· Integrated 57 kHz band-pass filter (8th order)
· Reconstruction filter (2nd order)
· Clocked comparator with automatic offset compensation
· 57 kHz carrier regeneration
· Synchronous demodulator for 57 kHz modulated RDS signals
· Selectable 4.332/8.664 MHz crystal oscillator with variable dividers
· Clock regeneration with lock on biphase data rate
· Biphase symbol decoder with integrate and dump functions
· Differential decoder
· Signal quality detector
· Subcarrier output.

SAA6579 Connection Diagram

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