R8810, R8810QF-C, R8820LV Selling Leads, Datasheet
MFG:4800 Package Cooled:QFP D/C:08+
R8810, R8810QF-C, R8820LV Datasheet download
Part Number: R8810
MFG: 4800
Package Cooled: QFP
D/C: 08+
R8810, R8810QF-C, R8820LV
- Table of contents:
Info of R8810
Info of R8810QF-C
Info of R8820LV
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About R880
PDF/DataSheet Download
Datasheet: R880
File Size: 450601 KB
Manufacturer: EPCOS
Download : Click here to Download
About R880
PDF/DataSheet Download
Datasheet: R880
File Size: 450601 KB
Manufacturer: EPCOS
Download : Click here to Download
About R8820LV
PDF/DataSheet Download
Datasheet: R8820LV
File Size: 1024006 KB
Manufacturer: ETC [ETC]
Download : Click here to Download
R8810 General Description
The R8810 is a 16-bit high-performance microprocessor designed with RDC embedded RISC architecture. It features PSRAM (Pseudo static RAM) interface with auto-refresh control, DMA controller, three independent 16-bit timer/watchdog timer, interrupt controller. It is also with the compatibility of 80C186 microprocessor.
R8820LV Features
·Five-stages pipeline
·RISC architecture
·Static Design & Synthesizable design
·Bus interface
- Multiplexed address and Data bus which is compatible with 80C186 microprocessor
- Supports nonmultiplexed address bus [A19 : A0]
- 1M byte memory address space
- 64K byte I/O space
·Software is compatible with the 80C186 microprocessor
·Support two Asynchronous serial channel with hardware handshaking signals.
·Supports 32 PIO pins
·PSRAM (Pseudo static RAM) interface with auto-refresh control
·Three independent 16-bit timers and one independent watchdog timer
·The Interrupt controller with seven maskable external interrupts and one nonmaskable external interrupt
·Two independent DMA channels
·Programmable chip-select logic for Memory or I/O bus cycle decoder
·Programmable wait-state generator
·Support serial port/ DMA transfers
·RISC architecture
·Static Design & Synthesizable design
·Bus interface
- Multiplexed address and Data bus which is compatible with 80C186 microprocessor
- Supports nonmultiplexed address bus [A19 : A0]
- 1M byte memory address space
- 64K byte I/O space
·Software is compatible with the 80C186 microprocessor
·Support two Asynchronous serial channel with hardware handshaking signals.
·Supports 32 PIO pins
·PSRAM (Pseudo static RAM) interface with auto-refresh control
·Three independent 16-bit timers and one independent watchdog timer
·The Interrupt controller with seven maskable external interrupts and one nonmaskable external interrupt
·Two independent DMA channels
·Programmable chip-select logic for Memory or I/O bus cycle decoder
·Programmable wait-state generator
·Support serial port/ DMA transfers
R8820LV Connection Diagram
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