QS5K2, QS5L919-160J, QS5LV919 Selling Leads, Datasheet
MFG:ROHM Package Cooled:SOT-153 D/C:0606+NOPB
QS5K2, QS5L919-160J, QS5LV919 Datasheet download
Part Number: QS5K2
MFG: ROHM
Package Cooled: SOT-153
D/C: 0606+NOPB
MFG:ROHM Package Cooled:SOT-153 D/C:0606+NOPB
QS5K2, QS5L919-160J, QS5LV919 Datasheet download
MFG: ROHM
Package Cooled: SOT-153
D/C: 0606+NOPB
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Datasheet: QS5K2
File Size: 62677 KB
Manufacturer: ROHM
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Datasheet: QS5.1
File Size: 461481 KB
Manufacturer:
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Datasheet: QS5LV919
File Size: 100711 KB
Manufacturer: IDT [Integrated Device Technology]
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Parameter |
Symbol |
Limits |
Unit | ||
Drain-source voltage |
VDSS |
30 |
V | ||
Gate-source voltage |
VGSS |
121 |
V | ||
Drain current | Continuous |
ID |
±2.0 |
A | |
Pulsed |
IDP*1 |
±8.0 |
A | ||
Source current |
Continuous |
IS |
0.8 |
A | |
Pulsed |
ISP*1 |
3.2 |
A | ||
Total power dissipation |
PD*2 |
1.25 |
W / TOTAL | ||
0.9 |
W / ELEMENT | ||||
Channel temperature |
Tch |
150 |
°C | ||
Range of storage temperature |
Tstg |
−55 to +150 |
°C |
*1 Pw10s, Duty cycle1%
*2 Mounted on a ceramic board
The QS5LV919 Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: 2xQ, Q0-Q4, Q5, Q/2. Careful layout and design ensure < 300 ps skew between the Q0-Q4, and Q/2 outputs. The QS5LV919 includes an internal RC filter which provides excellent jitter characteristics and eliminates the need for external components. Various combinations of feedback and a divide-by-2 in the VCO path allow applications to be customized for linear VCO operation over a wide range of input SYNC frequencies. The PLL can also be disabled by the PLL_EN signal to allow low frequency or DC testing. The LOCK output asserts to indicate when phase lock has been achieved. The QS5LV919 is designed for use in high-performance workstations, multiboard computers, networking hardware, and mainframe systems. Several can be used in parallel or scattered throughout a system for guaranteed low skew, system-wide clock distribution networks.
For more information on PLL clock driver products, see Application Note AN-227.
Symbol |
Rating |
Max |
Unit | |
VDD, AVDD |
Supply Voltage to Ground |
0.5 to +7 |
V | |
DC Input Voltage VIN |
0.5 to +5.5 |
V | ||
Maximum Power Dissipation (TA = 85°C) |
QSOP |
655 |
mW | |
PLCC |
770 |
mW | ||
TSTG |
Storage Temperature Range |
65 to +150 |
°C |