QS532806, QS532806AQ, QS532806ASO Selling Leads, Datasheet
MFG:IDT Package Cooled:SOP D/C:1000
QS532806, QS532806AQ, QS532806ASO Datasheet download
Part Number: QS532806
MFG: IDT
Package Cooled: SOP
D/C: 1000
QS532806, QS532806AQ, QS532806ASO
- Table of contents:
Info of QS532806
Info of QS532806AQ
Info of QS532806ASO
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About QS532806/A
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Datasheet: QS532806/A
File Size: 98291 KB
Manufacturer: IDT
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About QS532806AQ
PDF/DataSheet Download
Datasheet: QS532806AQ
File Size: 98291 KB
Manufacturer:
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About QS532806ASO
PDF/DataSheet Download
Datasheet: QS532806ASO
File Size: 98291 KB
Manufacturer:
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QS532806 General Description
The QS532806 clock driver/buffer circuit can be used for clock buffering schemes where low skew is a key parameter. The QS532806 offers two banks of five inverting outputs. Designed in IDT's proprietary CMOS process, these devices provide low propagation delay buffering with onchip skew of 0.7ns for same-transition, same-bank signals.
The QS532806 has on-chip series termination resistors for lower noise clock signals. The series resistor versions are recommended for driving unterminated lines with capacitive loading and other noise sensitive clock distribution circuits. These clock buffer products are designed for use in high-performance workstations, embedded and personal computing systems. Several devices can be used in parallel or scattered throughout a system for guaranteed low skew, system-wide clock distribution networks.
QS532806 Maximum Ratings
|
Rating |
Symbol |
Max |
unit |
|
Supply Voltage Range |
V CC1, VCC2 |
0.5 to +4.6
|
V |
|
Input Voltage Range |
VI (2)
|
0.5 to +5.5 |
V |
|
Voltage range applied to any output in the high or low state |
VO(2) |
0.5 to VDD + 0.5
|
V |
|
Input clamp current |
IIK (VI < 0)
|
50 |
mA |
|
Terminal Voltage with Respect to GND (inputs VIH 2.5, VIL 2.5) |
IOK (VO < 0 or VO > VDD) |
-50
|
mA |
|
Continuous Output Current |
IRES |
±100 |
mA |
|
Continuous Current |
VDD or GND |
65 to +150 |
mA |
|
Junction Temperature |
TSTG |
150 |
°C |
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Vcc Terminals.
3. All terminals except Vcc.
QS532806 Features
- JEDEC compatible LVTTL level
- 10 low skew clock outputs
- Monitor output
- Clock inputs are 5V tolerant
- Pinout and function compatible with
- 25W on-chip resistors for low noise
- Input hysteresis for better noise margin
- Guaranteed low skew:
· 0.7ns output skew (same bank)
· 0.9ns output skew (different bank)
· 1ns part-to-part skew
- Std. and A speed grades
- Available in QSOP and SOIC packages
- 10 low skew clock outputs
- Monitor output
- Clock inputs are 5V tolerant
- Pinout and function compatible with
- 25W on-chip resistors for low noise
- Input hysteresis for better noise margin
- Guaranteed low skew:
· 0.7ns output skew (same bank)
· 0.9ns output skew (different bank)
· 1ns part-to-part skew
- Std. and A speed grades
- Available in QSOP and SOIC packages
QS532806 Connection Diagram
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