QL3025, QL3025-0PF144C, QL3025-1PF144C Selling Leads, Datasheet
MFG:5000 Package Cooled:QFP D/C:04+
QL3025, QL3025-0PF144C, QL3025-1PF144C Datasheet download
Part Number: QL3025
MFG: 5000
Package Cooled: QFP
D/C: 04+
QL3025, QL3025-0PF144C, QL3025-1PF144C
- Table of contents:
Info of QL3025
Info of QL3025-0PF144C
Info of QL3025-1PF144C
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About QL3025
PDF/DataSheet Download
Datasheet: QL3025
File Size: 245366 KB
Manufacturer: QuickLogic
Download : Click here to Download
About QL3025-0PF144C
PDF/DataSheet Download
Datasheet: QL3025-0PF144C
File Size: 184711 KB
Manufacturer:
Download : Click here to Download
About QL3004
PDF/DataSheet Download
Datasheet: QL3004
File Size: 260981 KB
Manufacturer: QuickLogic
Download : Click here to Download
QL3025 General Description
The QL3025 is a 25,000 usable PLD gate member of the pASIC 3 family of FPGAs. pASIC 3 FPGAs are fabricated on a 0.35 m four-layer metal process using QuickLogic®'s patented ViaLink® technology to provide a unique combination of high performance, high density, low cost, and extreme ease-of-use.
The QL3025 contains 672 logic cells. With a maximum of 204 I/Os, the QL3025 is available in 144-pin TQFP, 208-pin PQFP, and 256-pin PBGA packages.
Software support for the complete pASIC 3 family, including the QL3025, is available through three basic packages. The turnkey QuickWorks package provides the most complete FPGA software solution from design entry to logic synthesis, to place and route,to simulation. The QuickToolsTM for Workstations package provides a solution for designers who use Cadence®, ExemplarTM, Mentor®, Synopsys®, Synplicity®, ViewlogicTM, AldecTM, or other third-party tools for design entry, synthesis, or simulation.
QL3025 Features
High Performance & High Density
• 25,000 Usable PLD Gates with 204 I/Os
• 300 MHz 16-bit Counters,400 MHz Datapaths
• 0.35 m four-layer metal non-volatile
Easy to Use / Fast Development Cycles
• 100% routable with 100% utilization and complete pin-out stability
• Variable-grain logic cells provide high performance and 100% utilization
• Comprehensive design tools include high quality Verilog/VHDL synthesisCMOS process for smallest die sizes
Advanced I/O Capabilities
• Interfaces with both 3.3 V and 5.0 V devices
• PCI compliant with 3.3 V and 5.0 V buses for -1/-2/-3/-4 speed grades
• Full JTAG boundary scan
• I/O Cells with individually controlled
Registered Input Path and Output Enables
Total of 204 I/O Pins
• 196 bidirectional input/output pins, PCI-compliant for 5.0 V and 3.3 V buses for -1/-2/-3/-4 speed grades
• Four High Drive input-only pins
• Four High Drive input-only/distributed network pins
Four Low-Skew Distributed Networks
• Two array clock/control networks available to the logic cell flip-flop clock, set and reset inputs - each driven by an input-only pin
• Two global clock/control networks available to the logic cell; F1, clock set, reset inputs and the input, I/O register clock, reset, and enable inputs as well as the output enable control - each driven by an input-only or I/O pin, or any logic cell output or I/O cell feedback
High Performance
• Input + logic cell + output total delays under 6 ns
• Data path speeds over 400 MHz
• Counter speeds over 300 MHz
• 25,000 Usable PLD Gates with 204 I/Os
• 300 MHz 16-bit Counters,400 MHz Datapaths
• 0.35 m four-layer metal non-volatile
Easy to Use / Fast Development Cycles
• 100% routable with 100% utilization and complete pin-out stability
• Variable-grain logic cells provide high performance and 100% utilization
• Comprehensive design tools include high quality Verilog/VHDL synthesisCMOS process for smallest die sizes
Advanced I/O Capabilities
• Interfaces with both 3.3 V and 5.0 V devices
• PCI compliant with 3.3 V and 5.0 V buses for -1/-2/-3/-4 speed grades
• Full JTAG boundary scan
• I/O Cells with individually controlled
Registered Input Path and Output Enables
Total of 204 I/O Pins
• 196 bidirectional input/output pins, PCI-compliant for 5.0 V and 3.3 V buses for -1/-2/-3/-4 speed grades
• Four High Drive input-only pins
• Four High Drive input-only/distributed network pins
Four Low-Skew Distributed Networks
• Two array clock/control networks available to the logic cell flip-flop clock, set and reset inputs - each driven by an input-only pin
• Two global clock/control networks available to the logic cell; F1, clock set, reset inputs and the input, I/O register clock, reset, and enable inputs as well as the output enable control - each driven by an input-only or I/O pin, or any logic cell output or I/O cell feedback
High Performance
• Input + logic cell + output total delays under 6 ns
• Data path speeds over 400 MHz
• Counter speeds over 300 MHz
QL3025 Connection Diagram
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